US 10,255,551 B2Granted

Mixed-signal circuitry for computing weighted sum computation

AssigneesThe Regents of the University of Michigan, Mythic, Inc.

InventorsDavid Alan Fick, Laura E. Fick, Skylar J. Skrzyniarz, Manar El-Chammas

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Abstract

An integrated circuit and method are provided for performing weighted sum computations. The circuit includes: a plurality of current generators interconnected and arranged into pairs, a positive summation node, a negative summation node, and an input generation circuit. For each pair of current generators, the control terminal of each element is electrically connected to an input node. One of the current generators has its drain connected to the positive summation node while the other current generation element has its drain connected to the negative summation node. The remaining terminals on both current generators are connected to a reference, which may be shared. Each pair of current generator source predetermined amounts of current onto the two summation nodes when the following conditions occur: the input node is at an activation voltage, and the two summation nodes are at a predetermined target voltage.

Claims19

Dependent claims

A mixed-signal circuit for computing a weighted sum computation, comprising:

a plurality of programmable current sources arranged in pairs, a first programmable current source in each pair of programmable current sources is configured to store a value indicative of a positive weight and a second programmable current source in each pair of programmable current sources is configured to store a value indicative of a negative weight, each programmable current source has an input terminal and an output terminal, such that output terminals of the first programmable current sources are electrically coupled together at a positive summation node and output terminals of the second programmable current sources are electrically coupled together at a negative summation node;
an input circuit electrically coupled to each pair of programmable current sources in the plurality of programmable current sources and operates to supply current to each pair of programmable current sources in the plurality of programmable current sources;
a comparison circuit electrically coupled to the positive summation node and the negative summation node, wherein the comparison circuit operates to compare voltages at the positive summation node and the negative summation node to each other and outputs a signal indicative of the comparison result;
a differential current circuit electrically coupled to the positive summation node and the negative summation node and operates to supply a current to each of the positive summation node and the negative summation node, where the current supplied to the positive summation node exhibits a difference with the current supplied to the negative summation node;
and
a controller interfaced with the differential current circuit and the comparison circuit, wherein the controller interacts with the differential current circuit to change magnitude of the difference between the current supplied to the positive summation node and the current supplied to the negative summation node.

3 more elements

An integrated circuit comprising:

a plurality of paired current sources, wherein a first current source and a second current source of each of the plurality of paired current sources being arranged in electrical communication, wherein each of the first current source and the second current source comprises a drain terminal, and a source terminal;
wherein each of the plurality of paired current sources includes a control terminal arranged in electrical communication with an input node;
a pair of current summation nodes comprising a first current summation node and a second current summation node,
wherein:
the source terminal of each of the first current source and of the second current source of each of the plurality of paired current sources is connected to a ground;
the drain terminal of the first current source of each of the plurality of paired current sources is arranged in electrical communication with the first current summation node and the drain terminal of the second current source of each of the plurality of paired current sources is arranged in electrical communication with the second current summation node;
a differential current circuit comprising differential current controller and two differential current sources, wherein the differential current controller is in operable control communication with the two differential current sources, wherein each of the two differential current sources is arranged in electrical communication with one of the first current summation node and the second current summation node;
a common-mode current circuit comprising a common-mode current controller and two common current sources, wherein the common-mode current controller is in operable control communication with the two common current sources, wherein each of the two common current sources is arranged in electrical communication with one of the first current summation node and the second current summation node;
and
a comparator circuit that is in electrical communication with a terminal end of the first current summation node and the second current summation node.

7 more elements

A method of using an integrated circuit, the method comprising:

supplying a voltage input signal to a control terminal of each of a plurality of paired current sources;
in response to the voltage input signal, generating at each of the plurality of paired current sources two differential currents, wherein a value of a difference between the two differential currents generated by each of the plurality of paired current sources varies, and wherein each of the two differential currents of each of the plurality of paired current sources is sourced to one of a first summation node and a second summation node;
identifying an average voltage value of the first current summation node and the second current summation node;
in response to identifying the average voltage value of the first current summation node and the second current summation node, setting the average voltage value of the first current summation node and the second current summation node to a predetermined target voltage by generating two common current signals and sources a first common current signal and a second common current signal of the two common current signals to each of the first current summation node and the second current summation node, respectively, wherein a magnitude and a direction of the two common current signals are equal;
generating two predetermined differential current signals having a same magnitude and opposite directions;
sourcing a first differential current and a second differential current of the two predetermined differential currents to the first current summation node and the second current summation node, respectively;
comparing a total summed current sourced from the first current summation node and a total summed current sourced from the second current summation node;
and
outputting an indicator when the total summed current sourced from the first current summation node and the total summed current sourced from the second current summation node are equal.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/890,402Filed 7 Feb 2018 · us provisional application
Priority: 7 Feb 2017
Published: US 2018/0247192 A130 Aug 2018
Granted: 9 Apr 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H03K 19/20
Logic circuits, i.e. having at least two inputs acting on one output ; Inverting circuits: characterised by logic function, e.g. AND, OR, NOR, NOT…
G06G 7/14
Arrangements for performing computing operations, e.g. operational amplifiers specially adapted therefor: for addition or subtraction
G06J 1/00
Hybrid computing arrangements
G06N 3/063
Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons: using electronic means