Layout pattern proximity correction through fast edge placement error prediction

A method of generating a look-up table (LUT) associating, for a plurality of features on a semiconductor substrate surface, values of one or more quantities characteristic of an edge placement error (EPE) with values of one or more quantities characteristic of an etch process, the features to be etched into a material stack on said substrate via a plasma-based etch process performed in a processing chamber under a set of process conditions, the method comprising:

• (a) receiving the set of process conditions and the material stack composition;
• (b) receiving a pattern of photoresist defining a set of features;
• (c1) calculating, using a computer system, a first etch process characteristic value, the first etch process characteristic value corresponding to a first quantity characteristic of the etch process, under the set of process conditions, of a first selected feature from the set of features, wherein calculating the first etch process characteristic is performed using a computer model that relates an etched feature profile on a semiconductor device to one or more process conditions in an etcher;
• (c2) calculating, using a computer system, a second etch process characteristic value, the second etch process characteristic value corresponding to the first characteristic of the etch process, under the set of process conditions, of a second selected feature from the set of features, wherein calculating the second etch process characteristic is performed using the computer model;
• and
• (d1) including a first entry in the LUT associated with an edge of the first selected feature, the first entry comprising:
• the first etch process characteristic value;
• and
• a first EPE-characteristic (EPC) value corresponding to a quantity characteristic of an EPE of the edge of the first selected feature, said first EPC value generated by running a computerized etch profile model (EPM) to simulate etching under the set of process conditions of the material stack as overlaid with at least the portion of the pattern of photoresist corresponding to the first selected feature;
• and
• (d2) determining to not include an entry in the LUT associated with an edge of the second selected feature and comprising the second etch process characteristic value, the determining based, at least in part, on the similarity of the second etch process characteristic value to the first etch process characteristic value,
• wherein a LUT produced using (d1) and (d2) provides a computationally more efficient tool for determining values of the one or more quantities characteristic of edge placement error (EPE) in comparison to the computer model that relates an etched feature profile on a semiconductor device to one or more process conditions.