Power amplification module
AssigneeMurata Manufacturing Co., Ltd.
InventorsSatoshi Arayashiki, Satoshi Goto
Life of this patent
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Abstract
Provided is a power amplification module that includes: a first transistor, a first signal being inputted to a base thereof; a second transistor, the first signal being inputted to a base thereof and a collector thereof being connected to a collector of the first transistor; a first resistor, a first bias current being supplied to one end thereof and another end thereof being connected to the base of the first transistor; a second resistor, one end thereof being connected to the one end of the first resistor and another end thereof being connected to the base of the second transistor; and a third resistor, a second bias current being supplied to one end thereof and another end thereof being connected to the base of the second transistor.
Claims7
A power amplification module comprising:
- a first transistor, wherein a first signal is inputted to a base of the first transistor;
- a second transistor, wherein the first signal is inputted to a base of the second transistor, and a collector of the second transistor is connected to a collector of the first transistor;
- a third transistor, wherein a first bias control voltage is supplied to a base of the third transistor, and a first bias current is outputted from an emitter of the third transistor;
- a fourth transistor, wherein a second bias control voltage is supplied to a base of the fourth transistor, and a second bias current is outputted from an emitter of the fourth transistor;
- a first resistor, wherein the first bias current is supplied to a first end of the first resistor, the first end of the first resistor is connected to the emitter of the third transistor, and a second end of the first resistor is connected to the base of the first transistor;
- a second resistor, wherein a first end of the second resistor is connected to the first end of the first resistor, the first end of the second resistor is connected to the emitter of the third transistor, and a second end of the second resistor is connected to the base of the second transistor;
- and
- a third resistor, wherein the second bias current is supplied to a first end of the third resistor, the first end of the third resistor is connected to the emitter of the fourth transistor, a second end of the third resistor is connected to the base of the second transistor,
- wherein a second signal obtained by amplifying the first signal is outputted from the collectors of the first and second transistors.
Dependencies are inferred from the claim text.