Differential logic with low voltage supply

A method, comprising:

• receiving a first differential logic signal using a first branch of a circuit, which first branch extends from a voltage supply terminal of the circuit as far as an earth terminal of the circuit and has at least one first differential transistor pair;
• receiving a second differential logic signal using a second branch of the circuit, which second branch extends from the voltage supply terminal to the earth terminal and has at least one second differential transistor pair;
• conducting a current flow between the first branch and the second branch via an interface comprising a first conductor with a first capacitor and a second conductor with a second capacitor;
• and
• outputting an output signal by the second branch.

A frequency divider circuit comprising:

• a clock input circuit comprising a first differential pair of transistors having control nodes coupled to a clock input, first load resistors coupled to output nodes of the first differential pair of transistors, and a first current source connected between a first common node of the first differential pair of transistors and an earth reference terminal;
• a first interface capacitor having a first terminal coupled to a first output node of the first differential pair of transistors, and a second interface capacitor having a first terminal coupled to a second output node of the first differential pair of transistors;
• a latch circuit comprising
• a second differential pair of transistors having a second common node coupled to a second terminal of the first interface capacitor,
• a second current source connected between the second common node of the second differential pair of transistors and the earth reference terminal,
• second load resistors coupled to output nodes of the second differential pair of transistors,
• a third differential pair of transistors having a third common node coupled to a second terminal of the second interface capacitor, the third differential pair of transistors cross-coupled to the second differential pair of transistors, and
• a third current source connected between the third common node of the third differential pair of transistors and the earth reference terminal.

A circuit, comprising:

• a voltage supply terminal;
• an earth terminal;
• a first input terminal configured to receive a first differential logic signal;
• a second input terminal configured to receive a second differential logic signal;
• a first branch, which extends from the voltage supply terminal to the earth terminal and has at least one first differential transistor pair, wherein the first branch is coupled to the first input terminal;
• a second branch, which extends from the voltage supply terminal to the earth terminal and has at least one second differential transistor pair, wherein the second branch is coupled to the second input terminal;
• an interface between the first branch and the second branch, said interface being configured to conduct a current flow between the first branch and the second branch;
• and
• an output terminal which is coupled to the second branch and which is configured to output an output signal,
• wherein the interface is coupled to the first branch between the voltage supply terminal and the at least one first differential transistor pair, and
• wherein the interface is coupled to the second branch between the earth terminal and the at least one second differential transistor pair.

A method of operating a frequency divider circuit comprising a clock input circuit comprising a first differential pair of transistors having control nodes coupled to a clock input, first load resistors coupled to output nodes of the first differential pair of transistors, and a first current source connected between a first common node of the first differential pair of transistors and an earth reference terminal;

• a first interface capacitor having a first terminal coupled to a first output node of the first differential pair of transistors, and a second interface capacitor having a first terminal coupled to a second output node of the first differential pair of transistors;
• a latch circuit comprising a second differential pair of transistors having a second common node coupled to a second terminal of the first interface capacitor, a second current source connected between the second common node of the second differential pair of transistors and the earth reference terminal, second load resistors coupled to output nodes of the second differential pair of transistors, a third differential pair of transistors having a third common node coupled to a second terminal of the second interface capacitor, the third differential pair of transistors cross-coupled to the second differential pair of transistors, and a third current source connected between the third common node of the third differential pair of transistors and the earth reference terminal, wherein the method comprises:
• receiving, at the clock input, a clock signal;
• and
• generating a divided clock signal at the output nodes of the second differential pair of transistors.

A method of operating a circuit, comprising a voltage supply terminal;

• an earth terminal;
• a first input terminal configured to receive a first differential logic signal;
• a second input terminal configured to receive a second differential logic signal;
• a first branch, which extends from the voltage supply terminal to the earth terminal and has at least one first differential transistor pair, wherein the first branch is coupled to the first input terminal;
• a second branch, which extends from the voltage supply terminal to the earth terminal and has at least one second differential transistor pair, wherein the second branch is coupled to the second input terminal;
• an interface between the first branch and the second branch, said interface being configured to conduct a current flow between the first branch and the second branch;
• and an output terminal which is coupled to the second branch and which is configured to output an output signal, wherein the interface is coupled to the first branch between the voltage supply terminal and the at least one first differential transistor pair, and wherein the interface is coupled to the second branch between the earth terminal and the at least one second differential transistor pair, the method comprising:
• receiving the first differential logic signal at the first input terminal;
• receiving the second differential logic signal at the second input terminal;
• and
• outputting the output signal by the output terminal.