Drive signal modulation method of modular multilevel converter and fault isolation method

A method of modulating a drive signal for a modular multilevel converter, the modular multilevel converter comprising at least one bridge arm, the bridge arm comprising at least one full-bridge submodule unit, the full-bridge submodule unit comprising a first power semiconductor switch, a second power semiconductor switch, a third power semiconductor switch and a fourth power semiconductor switch, the method comprising:

• the full-bridge submodule unit operates in two alternate operation modes, designated a first mode and a second mode;
• firstly enters the first mode, then enters the second mode, re-enters the first mode and so on;
• or firstly enters the second mode, then enters the first mode, re-enters the second mode and so on;
• in the first mode, an alternate drive signal is applied to the first power semiconductor switch and the second power semiconductor switch, such that the first power semiconductor switch and the second power semiconductor switch are turned on alternately in the same time sequence, while a complementary drive signal is applied to the third power semiconductor switch and the fourth power semiconductor switch, such that the third power semiconductor switch remains in an off state and the fourth power semiconductor switch remains in an on state in the time sequence of the alternate turning-on of the first power semiconductor switch and the second power semiconductor switch;
• and
• in the second mode, an alternate drive signal is applied to the third power semiconductor switch and the fourth power semiconductor switch, such that the third power semiconductor switch and the fourth power semiconductor switch are turned on alternately in the same time sequence, while a complementary drive signal is applied to the first power semiconductor switch and the second power semiconductor switch, such that the first power semiconductor switch remains in an on state and the second power semiconductor switch remains in an off state in the time sequence of the alternate turning-on of the third power semiconductor switch and the fourth power semiconductor switch.