Systems and methods for refreshing a memory bank while accessing another memory bank using a shared address path
AssigneeMicron Technology, Inc.
InventorJoosang Lee
Life of this patent
Estimating the term…
Abstract
A system includes multiple memory banks that store data. The system also includes an address path coupled to the memory banks that provides a row address to the memory banks. The system further includes a command address input circuit coupled to the address path that refreshes a first set of memory banks via the address path and, when the command address input circuit refreshes the first set of memory banks, activates a row of a second set of memory banks to store the data or read the data from the row of the second set of memory banks via the address path.
Claims21
A system comprising:
- a plurality of memory banks configured to store data, wherein the plurality of memory banks comprises a first set of memory banks and a second set of memory banks;
- an address path coupled to the plurality of memory banks, wherein the address path is configured to provide a row address to the plurality of memory banks;
- and
- a command address input circuit coupled to the address path, wherein the command address input circuit is configured to refresh the first set of memory banks via the address path and, when the command address input circuit refreshes the first set of memory banks, activate a row of the second set of memory banks to store the data or read the data from the row of the second set of memory banks via the address path.
A row address output circuit configured to:
- receive a first row address of a first set of memory banks of a plurality of memory banks, a second row address of a second set of memory banks of the plurality of memory banks, and a selection signal;
- output the first row address when the selection signal is associated with refreshing the plurality of memory banks or refreshing the first set of memory banks;
- and
- output the second row address when the selection signal is associated with refreshing the plurality of memory banks or refreshing the second set of memory banks, wherein the first set of memory banks is configured to be refreshed during activation of the second row of the second set of memory banks, wherein the second set of memory banks is configured to be refreshed during activation of the first row of the first set of memory banks.
A method comprising:
- receiving a command at a semiconductor device to refresh at least some memory banks of a plurality of memory banks of the semiconductor device;
- when the command is configured to refresh the plurality of memory banks of the semiconductor device, outputting a first row address of a first set of memory banks of the plurality of memory banks or a second row address of a second set of memory banks of the plurality of memory banks to be refreshed;
- when the command is configured to refresh the first set of memory banks and not the second set of memory banks, outputting the first row address of the first set of memory banks;
- and
- when the command is configured to refresh the second set of memory banks and not the first set of memory banks, outputting the second row address of the first set of memory banks.
Dependencies are inferred from the claim text.