Semiconductor memory device with late write feature
AssigneeRenesas Electronics Corporation
InventorToshihiko Funaki
Life of this patent
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Abstract
A stack memory includes a base chip, a memory chip stacked over the base chip, and a via 42 provided between the base chip and the memory chip. The base chip has an external interface circuit and a late write control circuit. The external interface circuit externally receives/transmits write data and read data. The late write control circuit has at least a register storing write data externally supplied through the external interface circuit. The memory chip has a memory cell array and a late write control circuit having at least a register storing write data supplied from the register through the via.
Claims10
A semiconductor memory device comprising:
- a base chip;
- a first memory chip which is stacked over the base chip;
- and
- a first through via which is provided between the base chip and the first memory chip, and is used for transmitting read data and write data,
- wherein the base chip has
- an external interface circuit which externally receives/transmits the write data and the read data, and
- a first late write control circuit which has a plurality of first registers storing the write data supplied externally through the external interface circuit and transferring a previous write data stored therein in response to a write command,
- wherein the first memory chip has
- a memory cell array which has a plurality of memory cells arranged in a matrix, and
- a plurality of second late write control circuits, each of which second late write control circuit has at least a second register storing the write data supplied from the first registers through the first through via and transferring the previous write data stored therein, and writes the previous write data output from the second register into a target memory cell for writing,
- wherein the first memory chip includes a plurality of memory banks of a same channel, a second late write control circuit is provided correspondingly to each one of the memory banks, a number of the first registers corresponds to a number of the memory banks, and
- wherein one of the first registers is selected, based on a bank address, and the data stored in the selected first register is transferred.
A semiconductor memory device, comprising:
- a base chip;
- a first memory chip which is stacked over the base chip;
- and
- a first through via provided between the base chip and the first memory chip,
- wherein the base chip comprises:
- an external interface circuit which externally receives/transmits write data and read data;
- and
- a first late write control circuit comprising a plurality of first registers storing the write data supplied externally through the external interface circuit and transferring previous write data stored therein in response to a write command, and
- wherein the first memory chip comprises:
- a memory cell array comprising a plurality of memory cells arranged in a matrix;
- and
- a plurality of second late write control circuits, each of the second late write control circuits comprising at least a second register storing a first write data supplied from the first register through the first through via, transferring previous second write data stored therein, and writing the second write data output from the second register into a target memory cell,
- wherein the first memory chip includes a plurality of memory banks of a same channel, one each of the second late write control circuits is provided for a corresponding one of the memory banks, a number of the first registers corresponding to a number of the memory banks, and
- wherein one of the first registers is selected, based on a bank address, and the data stored in the selected first register is transferred.
Dependencies are inferred from the claim text.