Partially and fully parallel normaliser
AssigneeImagination Technologies Limited
InventorTheo Alan Drane
Life of this patent
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Abstract
Hardware logic arranged to normalize (or renormalize) an n-bit input number is described in which at least a proportion of a left shifting operation is performed in parallel with a leading zero count operation. In various embodiments the left shifting and the leading zero count are performed independently. In various other embodiments, a subset of the bits output by a leading zero counter are input to a left shifter and the output from the left shifter is input to a renormalization block which completes the remainder of the left shifting operation independently of any further input from the leading zero counter.
Claims14
Hardware logic arranged to normalize an input binary number, the hardware logic comprising:
- a zero counter arranged to compute a number of leading or trailing zeros in the binary number;
- and
- normalization logic arranged to perform normalization of the binary number, the normalization comprising at least one shifting operation;
- wherein at least a portion of the normalization is performed in parallel with the computing of the number of leading or trailing zeros.
A method of normalizing an input binary number, the method comprising:
- computing, by hardware logic a number of leading or trailing zeros in the binary number in a zero counter;
- and
- normalizing the binary number in normalization logic, the normalization comprising at least one shifting operation and wherein at least a portion of the normalization is performed in parallel with the computing of the number of leading or trailing zeros.
A non-transitory computer readable storage medium having stored thereon computer executable program code that when executed causes at least one processor to:
- compute a number of leading or trailing zeros in a binary number in a zero counter;
- and
- normalize the binary number, the normalization comprising at least one shifting operation, wherein at least a portion of the normalization is performed in parallel with the computing of the number of leading or trailing zeros.
A non-transitory computer readable storage medium having stored thereon computer executable program code that, when executed at a computer system for generating a representation of a digital circuit from definitions of circuit elements and data defining rules for combining those circuit elements, cause the computer system to generate hardware logic arranged to normalize an input binary number, the hardware logic comprising:
- a zero counter arranged to compute a number of leading or trailing zeros in the binary number;
- and
- normalization logic arranged to perform normalization of the binary number, the normalization comprising at least one shifting operation,
- wherein at least a portion of the normalization is performed in parallel with the computing of the number of leading or trailing zeros.
Dependencies are inferred from the claim text.