US 10,222,421 B1Granted

Method for detecting faults on retention cell pins

AssigneeSilicon Laboratories Inc.

InventorsMudit Srivastava, Raghavendra Pai Kateel, Shantonu Bhadury

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Abstract

Embodiments are disclosed for systems and methods that include pulsing a clock pin of retention cells included within a scan chain to shift a sequence of logic values into the scan chain, so that successive cells are loaded with opposite logic values. Embodiments also include pulsing a retain pin to retain the logic values, and pulsing the clock pin to shift the sequence of logic values through the chain, so that retained logic values are output from, and logic values opposite to the retained logic values are loaded into, the cells. Embodiments also include pulsing a restore pin to restore the retained logic values, pulsing the clock pin to shift the logic values out of the scan chain, comparing the logic values shifted out of the scan chain with the logic values shifted into the scan chain, and detecting a fault on the retain pin based on said comparison.

Claims20

Dependent claims

A method for testing retention cells included within a scan chain, wherein each retention cell comprises a functional latch, a retention latch, a retain pin, a restore pin and a clock pin, and wherein the method comprises:

pulsing the clock pin of the retention cells to shift a sequence of logic values into the scan chain, so that successive retention cells are loaded with opposite logic values;
pulsing the retain pin of the retention cells to retain the logic values loaded into the retention cells;
pulsing the clock pin of the retention cells to shift the sequence of logic values through the scan chain, so that the retained logic values are output from the retention cells and logic values opposite to the retained logic values are loaded into the retention cells;
pulsing the restore pin of the retention cells to restore the retained logic values within the retention cells;
pulsing the clock pin of the retention cells to shift the sequence of logic values out of the scan chain;
comparing the sequence of logic values shifted out of the scan chain with the sequence of logic values shifted into the scan chain;
and
detecting a fault on the retain pin of one or more retention cells based on said comparison.

5 more elements

A computer-readable storage medium having a plurality of program instructions stored thereon, wherein the plurality of program instructions are executable by a processing device for testing retentions cells included within a scan chain, wherein each retention cell comprises a functional latch, a retention latch, a retain pin, a restore pin and a clock pin, and wherein the plurality of program instructions comprise:

first program instructions executable for pulsing the clock pin of the retention cells to shift a sequence of logic values into the scan chain, so that successive retention cells are loaded with opposite logic values;
second program instructions executable for pulsing the retain pin of the retention cells to retain the logic values loaded into the retention cells;
third program instructions executable for pulsing the clock pin of the retention cells to shift the sequence of logic values through the scan chain, so that the retained logic values are output from the retention cells and logic values opposite to the retained logic values are loaded into the retention cells;
fourth program instructions executable for pulsing the restore pin of the retention cells to restore the retained logic values within the retention cells;
fifth program instructions executable for pulsing the clock pin of the retention cells to shift the sequence of logic values out of the scan chain;
sixth program instructions executable for comparing the sequence of logic values shifted out of the scan chain with the sequence of logic values shifted into the scan chain;
and
seventh program instructions executable for detecting a fault on the retain pin of one or more retention cells based on said comparison.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/896,678Filed 14 Feb 2018
Granted: 5 Mar 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

G01R 31/318541
Using scanning techniques, e.g. LSSD, Boundary Scan, JTAG: scan latches or cell details
G01R 31/10
Locating faults in cables, transmission lines, or networks: by increasing destruction at fault, e.g. burning-in by using a pulse generator…
G01R 31/2813
Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing: checking the presence, location, orientation…
G01R 31/3177
Testing of digital circuits: testing of logic operation, e.g. by logic analysers