Pulse driven power FET

A power circuit, comprising:

• first and second power drive circuits, each configured to receive a plurality of pulse signals from a pulse generator, wherein each of the first and second power drive circuits comprises:
• a transformer, configured to generate first and second pulse signals;
• a pulse detector, configured to receive first and second pulse signals and to generate first and second control signals in response to the first and second pulse signals, respectively,
• a state storage device, configured to receive the first and second control signals and to generate first and second driver input signals in response to the first and second control signals, respectively, wherein the state storage device is configured to generate the first driver input signal in response to the first control signal and to maintain the first driver input signal until receiving the second control signal despite no longer receiving the first control signal, wherein the state storage device is configured to generate the second driver input signal in response to the second control signal and to maintain the second driver input signal until receiving the first control signal despite no longer receiving the second control signal,
• a driver configured to receive the first and second driver input signals and to generate first and second gate drive signals in response to the first and second driver input signals, respectively, and
• a power switch, configured to receive the first and second gate drive signals, wherein the first and second gate drive signals control the power switch to selectively conduct or not conduct current between first and second terminals, wherein the first gate drive signal causes the power switch to conduct and the second gate drive signal causes the power switch to not conduct,
• wherein the first control signal having a low logic state causes the state storage device to generate the first driver input signal.