US 10,177,773 B2 · Programmable clock divider

Abstract

In accordance with an embodiment, a circuit includes an input clock terminal, an output clock terminal, a first input data terminal, and a set of input data terminals having a number of terminals. A divide-by-two block is coupled to the output clock terminal. A modular one-shot clock divider is coupled between the input clock terminal and the divide-by-two block. The modular one-shot clock divider is further coupled to the set of input data terminals. An intermediate clock generation block is coupled between the input clock terminal and the modular one-shot clock divider. The intermediate clock generation block includes a first digital logic block coupled between the input clock terminal and the modular one-shot clock divider. The first digital logic block is further coupled to the first input data terminal, and a clock-blocking block is coupled between the divide-by-two block and the first digital logic block.

Claims21

Dependent claims

A circuit comprising:

an input clock terminal;
an output clock terminal;
a first input data terminal;
a set of input data terminals having a number of terminals, wherein the number of terminals is greater or equal to one, the first input data terminal being excluded from the set of input data terminals;
a divide-by-two block coupled to the output clock terminal;
a modular one-shot clock divider coupled between the input clock terminal and the divide-by-two block, the modular one-shot clock divider further coupled to the set of input data terminals;
and
an intermediate clock generation block coupled between the input clock terminal and the modular one-shot clock divider, the intermediate clock generation block comprising
a first digital logic block coupled between the input clock terminal and the modular one-shot clock divider, the first digital logic block further coupled to the first input data terminal, and
a clock-blocking block coupled between the divide-by-two block and the first digital logic block.

7 more elements

A circuit comprising:

an intermediate clock generator block configured to generate a first intermediate clock based on an input clock,
a modular one-shot divider configured to receive a first number of bits minus one most-significant-bits of a configuration word, the configuration word having the first number of bits, wherein the first number of bits minus one most-significant-bits of the configuration word have a first decimal equivalent number, the modular one-shot divider configured to generate a second intermediate clock based on the first intermediate clock, wherein generating the second intermediate clock comprises generating a one-shot pulse every first decimal equivalent number of first intermediate clock pulses, wherein the one-shot pulse comprises a transition from a first state to a second state and a transition from the second state to the first state;
and
a divide-by-two block configured to generate an output clock that toggles between a first state and a second state every one-shot pulse, wherein
when a least-significant-bit of the configuration word is zero, the intermediate clock generator block generates a clock pulse each time the input clock pulses, and
when the least-significant-bit of the configuration word is one, the intermediate clock generator block generates a clock pulse each time
the second intermediate clock is in the second state and the input clock pulses and
the second intermediate clock is in the first state, the output clock is in the first state and the input clock pulses.

5 more elements

Dependencies are inferred from the claim text.

Programmable clock divider

Life of this patent

Programmable clock divider

Life of this patent

Abstract

Claims21