Apparatus and method for updating operating system in programmable logic controller

An apparatus for updating an OS (Operating System) in a PLC (Programmable Logic Controller), the apparatus comprising:

• an MPU (Micro Processing Unit) downloading a plurality of OSs from a PADT (Programming And Debugging Tool) and performing an operation in response to the one of the downloaded OSs;
• a flash memory storing the plurality of downloaded OSs, wherein the flash memory includes a first OS area and a second OS area;
• a first working memory separate from and independent of the flash memory, wherein the first working memory stores a latest version of the plurality of OSs previously stored in the flash memory;
• a second working memory separate from and independent of the flash memory, wherein the second working memory stores a newly versioned OS in the flash memory subsequent to the first working memory storing the latest version of the plurality of OSs;
• and
• a switching unit configured to switch a chip select signal received from the MPU for selecting the first working memory or the second working memory in response to a chip switching signal received from the MPU and to apply the switched chip select signal to the first working memory and the second working memory, wherein switching the chip select signal reverses a previously applied chip select signal,
• wherein the PLC is operated by applying the newly versioned OS in the second working memory after the PLC was operated by applying the latest version of the plurality of OSs, wherein a switch of the operation of the PLC from the latest version of the plurality of OSs to the newly versioned OS is carried out without recycling power of the PLC,
• wherein the chip switching signal comprises a logic 1 signal and a logic 0 signal,
• wherein the chip select signal of the MPU comprises a first chip select signal and a second chip select signal,
• wherein the switching unit comprises:
• a first buffer and a second buffer configured to receive the first chip select signal of the MPU;
• and
• a third buffer and a fourth buffer configured to receive the second chip select signal of the MPU,
• wherein the chip switching signal outputted from the MPU is configured to be inputted to a non-inverting control terminal of the first buffer, a non-inverting control terminal of the third buffer, an inverting control terminal of the second buffer, and an inverting control terminal of the fourth buffer,
• wherein the first buffer and the fourth buffer are configured to output a chip select signal of the first working memory, wherein the chip select signal of the first working memory is configured to activate the first working memory, and
• wherein the second buffer and the third buffer are configured to output a chip select signal of the second working memory, wherein the chip select signal of the second working memory is configured to activate the second working memory.