US 10,122,568 B2Granted

Digital compensation of IQ coupling in communication receivers

AssigneeMicrochip Technology Incorporated

InventorsHamid Shafiee, Mohsen Pourkhaatoun, Kiran Gowda, Siddharth Shetty, Esmael Heidari, Ali Fard, Rahim Bagheri, Masoud Djafari

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Abstract

A receiver circuit includes a conversion circuit configured to down-convert a received radio-frequency signal to a baseband signal, an analog-to-digital converter configured to sample the baseband signal into a sampled signal, a Fast Fourier transform (FFT) circuit configured to perform an FFT on the sampled signal, and a digital compensation circuit configured to compensate for IQ distortion in a frequency domain.

Claims12

Dependent claims

A receiver circuit, comprising:

a conversion circuit configured to down-convert a received radio-frequency signal to a baseband signal;
an analog-to-digital converter configured to sample the baseband signal into a sampled complex time-domain signal;
and
a digital compensation circuit configured to compensate for in-phase and quadrature-phase (IQ) distortion in a frequency domain, wherein:
in a first branch:
the digital compensation circuit is further configured to multiply using a first multiplier circuit, the sampled complex time-domain signal by a first correction for carrier frequency offset to generate a first multiplied signal;
perform a first Fast Fourier transform (FFT) on the first multiplied signal through a first FFT circuit;
and
the digital compensation circuit is further configured to multiply using a second multiplier circuit, a result from the first FFT with a first factor to form a first output data;
in a second branch:
the digital compensation circuit is further configured to multiply using a third multiplier circuit, a complex baseband the sampled complex time-domain signal by a second correction for carrier frequency offset to generate a second multiplied signal;
perform a second FFT on the second multiplied signal through a second FFT circuit;
perform using an inversion and conjugation circuit, conjugation by inverting and conjugating an output of the second FFT;
and
the digital compensation circuit is further configured to multiply using a fourth multiplier circuit, the inverted and conjugated output of the second FFT with a second factor to form a second output data;
wherein, the first factor is λ1(ω)/δ and the second factor is λ2(ω)/δ, wherein
λ
1
⁡
(
ω
)
=
[
1
+
ω
+
Δω
2
⁢
(
β
1
-
β
2
)
]
,
⁢
λ
2
⁡
(
ω
)
=
[
-
ω
+
Δω
2
⁢
(
β
1
-
β
2
)
]
,
⁢
δ
=
λ
1
⁡
(
ω
)
⁢
λ
1
⁡
(
-
ω
-
2
⁢
Δω
)
-
λ
2
⁡
(
ω
)
⁢
λ
2
⁡
(
-
ω
-
2
⁢
Δω
)
,
and wherein ωΔ corresponds to a frequency offset, co corresponds to a frequency, Ts is a sampling period, and β1 and β2 are coupling coefficients;
and
the digital compensation circuit is further configured to add, by a summer circuit, the first output data and the second output data.

105 more elements

A system, comprising:

a conversion circuit configured to down-convert a received radio-frequency signal to a baseband signal;
an analog-to-digital converter configured to sample the baseband signal into a sampled complex time-domain signal;
and
a digital compensation circuit configured to compensate for in-phase and quadrature-phase (IQ) distortion in a frequency domain, wherein:
in a first branch:
the digital compensation circuit is further configured to multiply using a first multiplier circuit, the sampled complex time-domain signal by a first correction for carrier frequency offset to generate a first multiplied signal;
perform a first Fast Fourier transform (FFT) on the first multiplied signal through a first FFT circuit;
and
the digital compensation circuit is further configured to multiply using a second multiplier circuit, a result from the first FFT with a first factor to form a first output data;
in a second branch:
the digital compensation circuit is further configured to multiply using a third multiplier circuit, a complex baseband the sampled complex time-domain signal by a second correction for carrier frequency offset to generate a second multiplied signal;
perform a second FFT on the second multiplied signal through a second FFT circuit;
perform using an inversion and conjugation circuit, conjugation by inverting and conjugating an output of the second FFT;
and
the digital compensation circuit is further configured to multiply using a fourth multiplier circuit, the inverted and conjugated output of the second FFT with a second factor to form a second output data;
wherein, the first factor is λ1(ω) /δ and the second factor is λ2 (ω)/δ, wherein
λ
1
⁡
(
ω
)
=
[
1
+
ω
+
Δω
2
⁢
(
β
1
-
β
2
)
]
,
⁢
λ
2
⁡
(
ω
)
=
[
-
ω
+
Δω
2
⁢
(
β
1
-
β
2
)
]
,
⁢
δ
=
λ
1
⁡
(
ω
)
⁢
λ
1
⁡
(
-
ω
-
2
⁢
Δω
)
-
λ
2
⁡
(
ω
)
⁢
λ
2
⁡
(
-
ω
-
2
⁢
Δω
)
,
and wherein ωΔ corresponds to a frequency offset, ω corresponds to a frequency, Ts is a sampling period, and β1 and β2 are coupling coefficients;
and
the digital compensation circuit is further configured to add, by a summer circuit, the first output data and the second output data.

105 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/642,347Filed 6 Jul 2017 · us provisional application
Priority: 7 Jul 2016
Published: US 2018/0013605 A111 Jan 2018
Granted: 6 Nov 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H04L 27/3863
Using a non - coherent carrier, including systems with baseband correction for phase or frequency offset: compensation for quadrature error in the…
H04B 1/30
Circuits: for homodyne or synchrodyne receivers
H04L 1/0045
By using forward error control: arrangements at the receiver end
H04L 27/22
Phase-modulated carrier systems, i.e. using phase-shift keying: demodulator circuits; Receiver circuits

Family

Application62/359,372Us provisional application · filed 7 Jul 2016
US 2018/0013605 A1Pre-grant publication · published 11 Jan 2018
US 10,122,568 B2This patent

From the US filing history. Foreign family members aren’t listed.

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