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US 10,122,561 B2Granted
Orthogonal differential vector signaling codes with embedded clock
AssigneeKandou Labs, S.A.
InventorsBrian Holden, Amin Shokrollahi
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Abstract
Orthogonal differential vector signaling codes are described which support encoded sub-channels allowing transport of distinct but temporally aligned data and clocking signals over the same transport medium. Embodiments providing enhanced LPDDR interfaces are described which are suitable for implementation in both conventional high-speed CMOS and DRAM integrated circuit processes.
Claims20
A method comprising:
- receiving, at a plurality of multi-input comparators (MICs), a set of symbols of a codeword of a vector signaling code via wires of a multi-wire bus;
- generating a plurality of sub-channel data signals at a first subset of MICs of the plurality of MICs, each sub-channel data signal generated by a respective MIC of the first subset, the respective MIC applying a respective set of data input coefficients to the set of symbols of the codeword, the respective set of data input coefficients selected according to a respective row of a plurality of rows of an orthogonal matrix;
- and
- receiving first and second subsets of symbols of the set of the symbols of the codeword of the vector signaling code at a timing MIC of the plurality of MICs, the first and second subsets of the symbols received via first and second subsets of wires of the multi-wire bus, respectively;
- responsively generating, using the timing MIC, a sub-channel clock signal by applying a set of timing input coefficients to the first and second subsets of symbols of the set symbols to detect changes in common mode across the first subset of wires with respect to common mode across the second subset of wires, the changes in common mode associated with transitions in the sub-channel clock signal.
2 more elements
An apparatus comprising:
- a plurality of data multi-input comparators (MICs) configured to receive a set of symbols of a codeword of a vector signaling code via wires of a multi-wire bus, the plurality of data MICs configured to generate a plurality of sub-channel data signals, each sub-channel data signal generated by a respective data MIC of the plurality of data MICs, the respective data MIC applying a respective set of data input coefficients to the set of symbols of the codeword, the respective set of data input coefficients selected according to a respective row of a plurality of rows of an orthogonal matrix;
- and
- a timing MIC configured to receive first and second subsets of symbols of the set of the symbols of the codeword of the vector signaling code, the first and second subsets of the symbols received via first and second subsets of wires, respectively, the timing MIC further configured to responsively generate a sub-channel clock signal by applying a set of timing input coefficients to the first and second subsets of symbols of the set symbols to detect changes in common mode across the first subset of wires with respect to common mode across the second subset of wires, the changes in common mode associated with transitions in the sub-channel clock signal.
Dependencies are inferred from the claim text.