Signal phase tracking with high resolution, wide bandwidth and low phase noise using compound phase locked loop

A clock recovery circuit that recovers a timing signal from a bursty input signal where the input signal is periodically present and absent, said recovery circuit comprising:

• a main phase detector responsive to the input signal and a clock recovery signal and providing a phase error signal;
• an analog-to-digital (A/D) converter responsive to the phase error signal from the phase detector and converting the phase error signal to a digital phase error signal;
• a burst detector responsive to the input signal and detecting when the input signal is being received by the recovery circuit;
• a switch responsive to the digital phase error signal and being closed by the burst detector in response to detecting the presence of the input signal;
• a digital main loop filter responsive to the digital phase error signal and generating a digital tuning signal;
• and
• a numerically controlled oscillator (NCO) circuit responsive to a reference clock signal and the digital tuning signal, said NCO circuit including an inner phase locked loop (PLL) having an inner phase detector generating an inner error signal in response to the reference clock signal and a feedback clock recovery signal, a feedback divider responsive to the clock recovery signal that divides the clock recovery signal by a programmable value defined by the tuning signal to generate the feedback clock recovery signal, an NCO circuit loop filter that filters the inner error signal, a digital-to-analog (D/A) converter that converts the digital tuning signal to an analog tuning signal, an NCO circuit summer that adds the filtered inner error signal and the analog tuning signal and provides a summed signal, and an NCO circuit controlled oscillator that is tuned by the summed signal so as to generate the clock recovery signal.