Phase detector in a delay locked loop

An apparatus comprising:

• a reference clock;
• a feedback clock;
• a first cross coupled latch operable to set a first latch output depending on a lead-lag status between the reference clock and the feedback clock, wherein the lead-lag status indicates that the feedback clock leads the reference clock or that the feedback clock lags the reference clock;
• a second cross coupled latch that loads the lead-lag status when the reference clock and the feedback clock produce clock signals in a high state;
• and
• a third cross coupled latch that loads the lead-lag status from the second cross coupled latch to the third cross coupled latch when the reference clock and the feedback clock produce clock signals in a low state.

A method for performing phase detection, the method comprising:

• setting, in a first latch of a phase detector, a first latch output depending on a lead-lag status between a reference clock and a feedback clock in the phase detector;
• loading, in a second latch of the phase detector, the lead-lag status when the reference clock and the feedback clock produce clock signals in high states;
• and
• loading, in a third latch of the phase detector, the lead-lag status from the second latch when the reference clock and the feedback clock produce clock signals in low states.