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US 10,122,525 B2Granted
Method and apparatus for performing a holdover function on a holdover line card
AssigneeNokia of America Corporation
InventorsSimon P. Creasy, Steven G. Driediger
Life of this patent
Estimating the term…
Abstract
Various embodiments relate to a network node and method thereof including a high stability oscillator and a holdover phase-locked loop (“PLL”) wherein the holdover PLL is configured to perform a holdover function by receiving a system clock signal, disciplining the high stability oscillator using the system clock signal to generate a local reference signal, and providing the local reference signal as the system clock signal when the system clock signal becomes unavailable.
Claims20
A network node, comprising:
- a timing circuit comprising a phase lock loop (“PLL”) and a first oscillator, wherein the PLL is configured to generate a system clock signal based on source timing information and an output of the first oscillator;
- a holdover circuit comprising a second oscillator, the second oscillator having higher stability than the first oscillator, the holdover circuit using the system clock signal from the timing circuit to discipline the second oscillator and generate a local reference clock signal,
- wherein the local reference clock signal is used as the source timing information for the timing circuit to generate a disciplined system clock signal in response to which the holdover circuit does not discipline using the disciplined system clock signal.
A method for performing a holdover function on a network node, comprising the steps of:
- generating a system clock signal, by a phase lock loop (“PLL”) on a timing circuit including and a first oscillator, based on source timing information and an output of the first oscillator;
- disciplining, by a holdover circuit including a second oscillator, the second oscillator having higher stability than the first oscillator, the second oscillator using the system clock signal from the timing circuit and generating a local reference clock signal,
- wherein the local reference clock signal is used as the source timing information for the timing circuit to generate a disciplined system clock signal in response to which the holdover circuit does not discipline using disciplined the system clock signal.
Dependencies are inferred from the claim text.