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US 10,122,384 B2Granted
Logical interleaver
AssigneeArm Limited
InventorsLiangzhen Lai, Vikas Chandra, Gary Dale Carpenter
Life of this patent
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Abstract
Various implementations described herein are directed to a memory device. The memory device includes a first interleaving circuit that receives data words and generates a first error correction code based on the received data words. The memory device includes a second interleaving circuit that receives the data words and generates a second error correction code based on the received data words as a complement to the first error correction code. The second interleaving circuit interleaves data bits from multiple different data words and stores modified data words based on the multiple different data words.
Claims18
A memory device, comprising:
- a first interleaving circuit coupled to read and write ports, wherein the first interleaving circuit:
- receives data words from one or more of the read and write ports,
- physically interleaves the received data words, and
- generates a first error correction code based on the physical interleaving of the received data words;
- and
- a second interleaving circuit that is separate from and coupled to the first interleaving circuit, wherein the second interleaving circuit:
- receives the data words from the first interleaving circuit,
- logically interleaves the data words received from the first interleaving circuit, and
- generates a second error correction code based on the logical interleaving of the data words received from the first interleaving circuit as a complement to the first error correction code by interleaving data bits from multiple different data words and storing modified data words based on the multiple different data words,
- wherein the physical interleaving of the first interleaving circuit and the logical interleaving of the second interleaving circuit protect data stored in the memory device against multi-cell upset.
7 more elements
A memory circuit, comprising:
- a first interleaving circuit coupled to read and write ports, wherein the first interleaving circuit:
- receives binary coded words from one or more of the read and write ports,
- physically interleaves the received binary coded words, and
- generates a first error correction code based on the physical interleaving of the received binary coded words;
- and
- a second interleaving circuit that is separate from and coupled to the first interleaving circuit, wherein the second interleaving circuit:
- receives the binary coded words from the first interleaving circuit,
- logically interleaves the binary coded words received from the first interleaving circuit,
- generates a second error correction code based on the logical interleaving of the received binary coded words as a complement to the first error correction code, and
- stores modified binary coded words based on interleaved data bits from multiple different binary coded words,
- wherein the physical interleaving of the first interleaving circuit and the logical interleaving of the second interleaving circuit protect data stored in the memory circuit against multi-cell upset.
8 more elements
A method for reducing memory storage errors, the method comprising:
- receiving data words from one or more read and write ports with a first interleaver circuit that is coupled to the one or more read and write ports, the first interleaver circuit physically interleaving the received data words;
- receiving the data words from the first interleaver circuit with a second interleaver circuit that is coupled to the first interleaver circuit, the second interleaver circuit logically interleaving the data words received from the first interleaver circuit;
- generating a first error correction code with the first interleaver circuit based on the physical interleaving of the received data words;
- generating a second error correction code with the second interleaver circuit based on the logical interleaving of the received data words as a complement to the first error correction code by interleaving data bits from multiple different data words and storing modified data words based on the multiple different data words,
- wherein the second interleaver circuit is separate from the first interleaver circuit,
- wherein the physical interleaving of the first interleaver circuit and the logical interleaving of the second interleaving circuit protect stored data against multi-cell upset.
3 more elements
Dependencies are inferred from the claim text.