Digital-to-time converter and operating method thereof

A digital-to-time converter comprising:

• a first delay cell configured to generate a first clock signal based on at least one upper bit of a digital code, the first clock signal causing a delay of an input clock signal by a first delay amount;
• and
• a second delay cell configured to generate a second clock signal based on at least one lower bit of the digital code, the second clock signal causing delay of the first clock signal by a second delay amount, wherein
• the first delay cell comprises,
• a first digital-to-analog converter configured to generate a precharge voltage corresponding to a value of the at least one upper bit;
• a first ramp voltage generator configured to,
• generate a first ramp voltage whose voltage level changes from a voltage level of the precharge voltage to a first slope based on the precharge voltage, and
• output the first ramp voltage through a first output node;
• and
• a first comparator configured to
• generate the first clock signal based on a voltage level of the first ramp voltage and a voltage level of a first reference voltage.

A method of operating a digital-to-time converter, the method comprising:

• generating, by a first delay cell, a first clock signal which causes a delay of an input clock signal by a first delay amount based on at least one upper bit of a digital code;
• and
• generating, by a second delay cell, a second clock signal which causes a delay of the first clock signal by a second delay amount based on at least one lower bit of the digital code, wherein
• the generating of the first clock signal comprises,
• precharging a first load capacitor provided in the first delay cell based on a precharge voltage corresponding to a value of the at least one upper bit,
• setting a voltage level of a second node connected to a first current source such that the first current source generates a reference current, and
• discharging a constant current based on the reference current from the first load capacitor.