Comparator, circuit device, physical quantity sensor, electronic device, and vehicle

A comparator comprising:

• a first voltage-time conversion circuit which includes a first delay circuit, the first delay circuit being configured to receive a first input signal and a second input signal;
• a second voltage-time conversion circuit which includes a second delay circuit, the second delay circuit being configured to receive the first input signal and the second input signal;
• and
• a determination circuit communicating with the first and second voltage-time conversion circuits, the determination circuit being configured to determine a magnitude relation of the first input signal and the second input signal, based on an output signal of the first voltage-time conversion circuit and an output signal of the second voltage-time conversion circuit,
• wherein the first delay circuit includes a first delay unit, the first delay unit including:
• a first primary conductivity type transistor, a current of the first primary conductivity type transistor being controlled based on the first input signal,
• a first secondary conductivity type transistor, a current of the first secondary conductivity type transistor being controlled based on the second input signal, and
• a first delay buffer circuit connected to the first primary conductivity type transistor and the first secondary conductivity type transistor, the first delay buffer circuit being configured to delay an input signal received by the first delay unit and generate a first delayed output signal based on the first input signal and the second input signal, and
• wherein the second delay circuit includes a second delay unit, the second delay unit including:
• a second primary conductivity type transistor, a current of the second primary conductivity type transistor being controlled based on the second input signal,
• a second secondary conductivity type transistor, a current of the second secondary conductivity type transistor being controlled based on the first input signal, and
• a second delay buffer circuit connected to the second primary conductivity type transistor and the second secondary conductivity type transistor, the second delay buffer circuit being configured to delay an input signal received by the second delay unit and generate a second delayed output signal based on the first input signal and the second input signal.