Reference precharge techniques for analog-to-digital converters
AssigneeAnalog Devices Global
InventorsAnoop Manissery Kalathil, Arvind Madan, Sandeep Monangi
Life of this patent
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Abstract
Systems and methods to reduce the amount of reference current drawn by a SAR ADC by including an auxiliary or precharge reference source. The ADC can connect the bit trial capacitors of a main digital-to-analog converter (DAC) to an auxiliary or precharge reference source during the loading of the bit trials, and then the ADC can switch to a main reference buffer. After allowing enough time for both phases, the main DAC can proceed with the bit trials to resolve the remaining bits. The rest of the bit trials can be performed directly using the main reference buffer.
Claims29
A method of operating a successive approximation register (SAR) analog-to-digital converter (ADC) circuit to precharge a bit trial capacitor of a main ADC, the method comprising:
- determining a bit trial result using an auxiliary ADC, the auxiliary ADC configured to resolve K bits of an N-bit digital word;
- loading the bit trial result onto the bit trial capacitor of the main ADC;
- connecting a first plate of the bit trial capacitor in the main ADC to a first reference voltage for a first time, the bit trial capacitor representing a bit of the K bits, the main ADC configured to resolve the remaining bits of the N-bit digital word;
- and
- after the first time, disconnecting the first plate of the bit trial capacitor from the first reference voltage and connecting the first plate of the bit trial capacitor to a second reference voltage for a second time.
A successive approximation register (SAR) analog-to-digital converter (ADC) circuit for precharging a bit trial capacitor of a main ADC, the circuit comprising:
- an auxiliary ADC configured to resolve K bits of an N-bit digital word;
- a main ADC configured to resolve the remaining bits of the N-bit digital word, the main ADC including:
- the bit trial capacitor representing a bit of the N-bit digital word;
- first and second electronic switches coupled to a plate of the bit trial capacitor;
- and
- control circuitry configured to:
- determine a bit trial result using the auxiliary ADC;
- load the at least one bit trial result onto the bit trial capacitor of the main ADC;
- control the first electronic switch to connect the first plate of the bit trial capacitor of the main ADC to one of a first positive reference voltage or a first negative reference voltage for a first time based on the bit trial result of the auxiliary ADC;
- and
- after the first time, control the first electronic switch to disconnect the first plate of the bit trial capacitor from the first positive reference voltage or the first negative reference voltage and control the second electronic switch to connect the first plate of the bit trial capacitor to one of a second positive reference voltage or a second negative reference voltage for a second time based on the bit trial result.
A method of operating a successive approximation register (SAR) analog to digital converter (ADC) integrated circuit device to precharge bit trial capacitors of a main ADC, the method comprising:
- determining a first plurality of bit trial results using an auxiliary ADC;
- loading the first plurality of bit trial results onto the bit trial capacitors of the main ADC;
- connecting respective first plates of a corresponding first plurality of capacitors in the main ADC to one of a first positive reference voltage or a first negative reference voltage for a first time, based on the bit trial results, wherein the first plurality of capacitors represent a first plurality of bits of a digital word;
- during the first time, determining a second plurality of bit trial results using the auxiliary ADC;
- loading the second plurality of bit trial results onto the bit trial capacitors of the main ADC;
- after the first time, connecting respective first plates of a corresponding second plurality of capacitors in the main ADC to one of the first positive reference voltage or the first negative reference voltage for a second time, based on the bit trial results, wherein the second plurality of capacitors represent a second plurality of bits of a digital word;
- and
- after the second time, disconnecting the first plates of the first and second plurality of capacitors in the main ADC from the first positive reference voltage or the first negative reference voltage and connecting the first plates of the first and second plurality of capacitors in the main ADC to one of a second positive reference voltage or a second negative reference voltage, based on the second plurality of bit trial results.
A method of operating a successive approximation register (SAR) analog-to-digital converter (ADC) circuit to precharge bit trial capacitors, the method comprising:
- determining K bit trial results of an N-bit digital word using a digital-to-analog converter (DAC) circuit;
- connecting first plates of corresponding respective K bit trial capacitors in the DAC circuit to a first reference voltage for a first time, each of the K bit trial capacitors representing a bit of the N bits;
- after the first time, disconnecting first plates of the K bit trial capacitors from the first reference voltage and connecting the first plates of the corresponding respective K bit trial capacitors to a second reference voltage for a second time;
- determining the remaining (N-K) bit trial results of the N-bit digital word using the DAC circuit;
- and
- connecting first plates of corresponding respective (N-K) bit trial capacitors in the DAC circuit to the second reference voltage.
A successive approximation register (SAR) analog-to-digital converter (ADC) circuit for precharging bit trial capacitors, the circuit comprising:
- a digital-to-analog converter (DAC) circuit configured to resolve N bits of an N-bit digital word, the DAC circuit including:
- bit trial capacitors representing bits of the N-bit digital word;
- electronic switches coupled to first plates of corresponding respective hit ial capacitors;
- and control circuitry configured to:
- determine K bit trial results of the N-bit digital word using the DAC circuit;
- control the electronic switches to connect first plates of corresponding respective l bit trial capacitors in the DAC circuit to a first reference voltage for a first time, each of the K bit trial capacitors representing a bit of the N bits;
- after the first time, control the electronic switches to disconnect first plates of the K bit trial capacitors from the first reference voltage and connect the first plates of the corresponding respective K bit trial capacitors to a second reference voltage for a second time;
- determine the remaining(N-K) bit trial results of the N-bit digital word using the DAC circuit;
- and
- control the electronic switches to connect first plates of corresponding respective (N-K) bit trial capacitors in the DAC circuit to the second reference voltage.
Dependencies are inferred from the claim text.