Circuit including calibration for offset voltage compensation

A switching digital-to-analog converter (DAC), comprising:

• a plurality of parallel switching paths having a corresponding plurality of inputs for respectively receiving digital data of an differential digital input signal;
• and
• an output summer for summing analog outputs respectively provided by the plurality of parallel switching paths to provide a differential analog output signal corresponding to the differential digital input signal,
• wherein each switching path of the plurality of parallel switching paths comprises:
• a logic gate for receiving the respective digital data of the differential digital input signal, the respective digital data having an input pulse with a corresponding input pulse width, and for outputting a mismatched input signal having a mismatched pulse with a corresponding mismatched pulse width different from the input pulse width, resulting from a voltage offset introduced by the logic gate;
• a direct current (DC) voltage source for providing a DC calibration signal;
• a unit DAC driver comprising a summer and a limiting buffer, the summer for summing the DC calibration signal and the mismatched input signal as digital input to compensate for at least the voltage offset introduced by the logic gate, and the limiting buffer for buffering the summed DC calibration signal and the mismatched input signal to provide a corrected input signal having a corrected pulse with a corresponding corrected pulse width that is the same as the input pulse width;
• and
• a unit DAC driven by the corrected input signal from the unit DAC driver to provide respective analog data corresponding to the switching path, and to selectively switch the respective analog data to the output summer.

A switching digital-to-analog converter (DAC), comprising:

• a plurality of parallel switching paths having a corresponding plurality of input ports for respectively receiving digital data of a differential digital input signal;
• and
• an output summer for summing analog outputs respectively output by the plurality of parallel switching paths to provide a differential analog output signal corresponding to the differential digital input signal,
• wherein each switching path of the plurality of parallel switching paths comprises:
• a logic gate for receiving the respective digital data of the differential digital input signal, the respective digital data having an input pulse defined by a rising edge and a corresponding falling edge following a first delay from the rising edge, and for outputting a mismatched input signal having a mismatched pulse defined by a rising edge and a corresponding falling edge following a second delay, wherein the second delay is different than the first delay as a result of a voltage offset introduced by the logic gate;
• a direct current (DC) voltage source for providing a DC calibration signal;
• a summer configured to sum the DC calibration signal and the mismatched input signal to compensate for at least the voltage offset introduced by the logic gate, and to provide a corrected input signal having a corrected pulse defined by a rising edge and a corresponding falling edge following a third delay, wherein the third delay is equal to the first delay;
• a limiting buffer configured to buffer the corrected input signal;
• and
• a unit DAC driven by the buffered corrected input signal output by the limiting buffer as digital input to provide a corresponding analog output, and to selectively switch the analog output from the switching path to the output summer.