Compact high speed duty cycle corrector

A communication system comprising:

• a signal processing module being configured to equalize a data signal;
• a clock data recovery (CDR) device being configured to generate a first clock signal based on the equalized data signal;
• a duty cycle correction (DCC) device being configured to generate a corrected clock signal based on the first clock signal, wherein the DCC device comprises:
• an input terminal for receiving the first clock signal;
• a first pair of transistors being configured to receive the first clock signal via the input terminal and to output a second clock signal, the first pair transistor comprises a PMOS transistor and an NMOS transistor;
• an output node being coupled to the second clock signal;
• a duty cycle sensor being configured to generate a first correction signal based on the second clock signal;
• and
• a duty cycle corrector being configured to generate a second correction signal based on the first correction signal, the second correction signal being coupled to the output node.

A method for correcting clock duty cycles, the method comprising:

• processing an input clock signal using a first pair of transistors, the input clock signal being characterized by a first duty cycle;
• providing an output clock signal using the first pair of transistors;
• generating a first correction signal by at least inverting a portion of the output clock signal;
• receiving a duty cycle control value;
• converting the duty cycle control value to a control voltage;
• providing a control signal by a second pair of transistors;
• generating a second correction signal by a third pair of transistors using the control signal and the first correction signal, the second correction being associated with a rise or fall time;
• and
• applying the second correction signal to the output clock signal, the output clock signal being characterized by a second duty cycle, the second duty cycle being closer to 50% than the first duty cycle.