Back to results
US 10,122,347 B2Granted
Adaptive voltage system for aging guard-band reduction
AssigneeIntel Corporation
InventorsMinki Cho, Jaydeep Kulkarni, Carlos Tokunaga, Muhammad Khellah, James Tschanz
Life of this patent
Estimating the term…
Abstract
An apparatus is provided which includes: a first power supply node; a second power supply node; a memory bit-cell coupled to the second power supply node; a circuitry coupled to the first and second power supply nodes, the circuitry to operate in a diode-connected mode; and a transistor coupled in parallel to the circuitry, wherein the transistor is controllable by a digital signal such that when the transistor is to turn on, it is to apply voltage and/or current stress to the memory bit-cell.
Claims18
An apparatus comprising:
- a first power supply node;
- a second power supply node;
- a memory bit-cell coupled to the second power supply node;
- circuitry coupled to the first and second power supply nodes, wherein the circuitry is to operate in a diode-connected mode;
- a transistor coupled in parallel to the circuitry, wherein the transistor is controllable by a digital signal such that when the transistor is to turn on, it is to apply voltage and/or current stress to the memory bit-cell;
- and
- a sense amplifier to determine a logic state stored in the memory bit-cell before and after the application of the voltage and/or current stress to the memory bit-cell, wherein an output of the sense amplifier is to indicate an early detection of memory failure during a standby or retention mode.
4 more elements
An apparatus comprising:
- a first power supply node;
- and
- a retention Vmin monitor (RVM) coupled to a memory, wherein the RVM is to detect an aging failure of the memory, wherein the RVM and the memory are coupled to the first power supply node, and wherein the RVM comprises:
- a bit-cell coupled to a second power supply node;
- circuitry coupled to the first and second power supply nodes, wherein the circuitry is to operate in a diode-connected mode;
- and
- a transistor coupled in parallel to the circuitry, wherein the transistor is controllable by a digital signal such that when the transistor is to turn on, it is to apply voltage and/or current stress to the bit-cell.
4 more elements
A system comprising:
- a voltage regulator;
- a power management circuitry coupled to the voltage regulator;
- a first power supply node coupled to the voltage regulator;
- and
- a processor coupled to the first power supply node and the power management circuitry, wherein the processor includes a memory having a memory bit-cell coupled to the first and second power supply nodes, wherein the processor comprises:
- a circuitry coupled to the first and second power supply nodes, the circuitry to operate in a diode-connected mode;
- a transistor coupled in parallel to the circuitry, wherein the transistor is controllable by a digital signal such that when the transistor is to turn on, it is to apply voltage and/or current stress to the memory bit-cell;
- and
- a sense amplifier to determine a logic state stored in the memory bit-cell before and after the application of the voltage and/or current stress to the memory bit-cell, wherein an output of the sense amplifier is to indicate an early detection of failure of the memory during a standby or retention mode.
6 more elements
Dependencies are inferred from the claim text.