Auto-bias circuit for stacked FET power amplifier

A circuitry comprising:

• a supply node, a control node, an input node, an output node, and a fixed voltage node;
• an auto-bias circuit comprising a dividing circuit and an averaging circuit, wherein:
• the dividing circuit is coupled between the control node and the fixed voltage node, and configured to provide a first pre-gate signal having a first pre-gate voltage that has a fractional relationship with a control voltage of a control signal applied at the control node;
• and
• the averaging circuit is coupled between the supply node and the control node, and configured to provide a second pre-gate signal having a second pre-gate voltage that has a fractional relationship with a sum of the control voltage and a supply voltage of a supply signal provided at the supply node;
• a stacked power amplifier coupled between the supply node and the fixed voltage node, and comprising a first field-effect transistor (FET) coupled in series with a second FET, wherein a drain of the first FET is coupled to a source of the second FET;
• a first conditioning circuit configured to receive the first pre-gate signal and provide a first gate signal to a gate of the first FET;
• and
• a second conditioning circuit configured to receive the second pre-gate signal and provide a second gate signal to a gate of the second FET, wherein an input signal that is from the input node and provided to at least one of the first conditioning circuit and the second conditioning circuit causes an output signal at the output node that is coupled to a drain of the second FET.