Active gate clamping for inverter switching devices with enhanced common source inductance

A power converter comprising:

• a DC link with positive and negative buses configured to receive a DC supply voltage;
• a plurality of phase legs in a bridge configuration coupled between the positive and negative buses, each phase leg having series-connected upper and lower transistors with an intermediate junction providing a phase leg output;
• and
• upper and lower gate drive circuits for each phase leg supplying gate drive signals to the upper and lower transistors, respectively, wherein each drive circuit includes an active clamp for deactivating the upper and lower transistors, respectively;
• wherein the transistors are comprised of semiconductor devices and each having respective gate, source, and emitter terminals;
• wherein each emitter terminal is connected to a respective output electrode structured to enhance a common source inductance between the respective gate and emitter terminals;
• wherein each emitter terminal is further connected to a respective Kelvin emitter electrode substantially bypassing the output electrode structure;
• and
• wherein each respective active clamp is connected between the respective gate terminal and Kelvin emitter electrode.

An inverter comprising;

• a bridge having upper and lower transistors;
• and
• upper and lower gate drive circuits including active clamps for deactivating the transistors;
• wherein each transistor has an output electrode structured to enhance a common source inductance of the transistor;
• wherein each transistor has a Kelvin emitter electrode substantially bypassing the respective output electrode;
• and
• wherein each active clamp is connected between a gate terminal and Kelvin emitter electrode of the respective transistor.