Cycle skipping prevent circuit in a regulator of a DC-to-DC converter

A voltage regulator control circuit for controlling a DC-to-DC switching converter, wherein the voltage regulator control circuit comprises:

• a sequential logic element having a set input lead, a reset input lead, and an output lead;
• a comparator circuit that has a first input lead, a second input lead, and an output lead, wherein the first input lead receives a voltage signal VCURRENT, wherein the voltage signal VCURRENT is indicative of a current flow in the DC-to-DC switching converter;
• a flip-flop having an oscillator signal input lead, a data input lead, and a data output lead;
• first logic gate circuitry having a first input lead, a second input lead, and an output lead, wherein the second input lead of the first logic gate circuitry is coupled to the data output lead of the flip-flop;
• second logic gate circuitry having a first input lead, a second input lead, and an output lead, wherein the second input lead of the second logic gate circuitry is coupled to receive a first signal from the output lead of the first logic gate circuitry, wherein the first input lead of the second logic gate circuitry is coupled to receive a second signal from the output lead of the comparator circuit, wherein the output lead of the second logic gate circuitry is coupled to supply a third signal onto the reset input lead of the sequential logic element;
• a delay element having an input lead and an output lead, wherein the output lead of the delay element is coupled to supply a fourth signal onto the set input lead of the sequential logic element;
• and
• a signal conductor that is coupled to the oscillator signal input lead of the flip-flop and to the first input lead of the first logic gate circuitry and to the input lead of the delay element.

A voltage regulator control circuit for controlling a DC-to-DC switching converter, wherein the voltage regulator control circuit comprises:

• a sequential logic element having a set input lead, a reset input lead, and an output lead;
• a comparator circuit that has a first input lead, a second input lead, and an output lead, wherein the first input lead receives a voltage signal VCURRENT, wherein the voltage signal VCURRENT is indicative of a magnitude of a current flowing in the DC-to-DC switching converter, wherein the comparator circuit outputs a RESET0 signal onto the comparator output lead;
• a signal conductor, wherein an oscillator signal OSC is present on the signal conductor;
• and
• means for receiving the RESET0 signal and for receiving the oscillator signal OSC, wherein the means is also for supplying a delayed version of the oscillator signal OSC onto the set input lead of the sequential logic element in a form of a signal SET, wherein the signal SET has a period that extends from a rising leading edge of a high pulse of the signal SET to a rising leading edge of a subsequent high pulse of the signal SET, wherein the means is also for gating a digital logic high signal as output by the comparator circuit onto the set input lead of the sequential logic element if the RESET0 signal as output by the comparator circuit is at a digital logic high level, wherein in the period if the RESET0 signal has not transitioned to the digital logic high level by a predetermined time in the period then the means gates the high pulse onto the set input lead of the sequential logic element.

A voltage regulator control circuit for controlling a DC-to-DC switching converter using a peak current (PC) mode, wherein the voltage regulator control circuit is an integrated circuit, wherein the DC-to-DC switching converter comprises an inductor, wherein a switching current ISW flows through the inductor, and wherein the voltage regulator control circuit comprises:

• a sequential logic element having a set input lead, a reset input lead, and an output lead;
• a first signal conductor that carries a voltage signal VCURRENT, wherein the voltage signal VCURRENT is indicative of a magnitude of the switching current ISW;
• a comparator circuit that has a first input lead, a second input lead, and an output lead, wherein the first input lead receives the voltage signal VCURRENT and that outputs a RESET0 signal onto the comparator output lead;
• a second signal conductor that carries an oscillator signal OSC;
• and
• a cycle skipping prevent circuit that receives the RESET0 signal and that receives the oscillator signal OSC, wherein the cycle skipping prevent circuit supplies a delayed version of the oscillator signal OSC onto the set input lead of the sequential logic element in a form of a signal SET, wherein the signal SET has a period that extends from a rising leading edge of a high pulse of the signal SET to a rising leading edge of a subsequent high pulse of the signal SET, wherein the cycle skipping prevent circuit gates a digital logic high signal as output by the comparator circuit onto the reset input lead of the sequential logic element if the RESET0 signal as output by the comparator circuit is at a digital logic high level, wherein in the period if the RESET0 signal has not transitioned to the digital logic high level by a predetermined time in the period then the cycle skipping prevent circuit gates the high pulse onto the reset input lead of the sequential logic element.