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US 10,121,959 B1Granted
FDSOI STT-MRAM design
AssigneeGlobalfoundries Singapore Pte. Ltd.
InventorsYinjie Ding, Eng Huat Toh, Kangho Lee, Elgin Kiok Boone Quek
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Abstract
A method of forming a segmented FDSOI STT-MRAM using dummy WL blocks and the resulting device are provided. Embodiments include forming a plurality of FDSOI STT-MRAM active WL blocks laterally separated across a memory array; forming a FDSOI STT-MRAM dummy WL block parallel to and on opposite sides of each active WL block; forming a plurality of SL structures laterally separated across the memory array; forming a plurality of BL structures laterally separated across the memory array; and connecting the plurality of SL and BL structures to the plurality of active WL blocks.
Claims17
A method comprising:
- forming a plurality of fully depleted silicon-on-insulator spin-transfer torque magnetoresistive random-access memory (FDSOI STT-MRAM) active word line (WL) blocks laterally separated across a memory array, each active WL block formed by:
- forming a n-type well (NW);
- forming a n-type ground plane (GP-N) layer over the NW;
- forming a buried oxide (BOX) layer over the GP-N layer;
- forming a silicon (Si) layer over the BOX layer;
- forming two pairs of two gates laterally separated over the Si layer;
- forming a shallow trench isolation (STI) region through the Si, BOX, and GP-N layers and a portion of the NW on opposite sides of each pair of gates;
- forming a n-type lightly dope drain (nLDD) in the Si layer on opposite sides and under a portion of each gate;
- and
- forming a n-type raised source/drain (nRSD) over each nLDD adjacent to and on opposite sides of each gate;
- forming a FDSOI STT-MRAM dummy WL block parallel to and on opposite sides of each active WL block;
- forming a plurality of source line (SL) structures laterally separated across the memory array;
- forming a plurality of bit line (BL) structures laterally separated across the memory array;
- and
- connecting the plurality of SL and BL structures to the plurality of active WLblocks.
12 more elements
A device comprising:
- a plurality of fully depleted silicon-on-insulator spin-transfer torque magnetoresistive random-access memory (FDSOI STT-MRAM) active word line (WL) blocks laterally separated across a memory array, wherein each active WL block comprises:
- a n-type well (NW);
- a n-type ground plane (GP-N) layer over the NW;
- a buried oxide (BOX) layer over the GP-N layer;
- a silicon (Si) layer over the BOX layer;
- two pairs of two gates laterally separated over the Si layer;
- a shallow trench isolation (STI) region through the Si layer, BOX, and GP-N layers and a portion of the NW on opposite sides of each pair of gates;
- a n-type lightly dope drain (nLDD) in the Si layer on opposite sides and under a portion of each gate;
- and
- a n-type raised source/drain (nRSD) over each nLDD adjacent to and on opposite sides of each gate;
- a FDSOI STT-MRAM dummy WL block parallel to and on opposite sides of each active WL block;
- a plurality of source line (SL) structures laterally separated across the memory array;
- and
- a plurality of bit line (BL) structures laterally separated across the memory array,
- wherein each SL and BL structure is connected to the plurality of active WL blocks.
12 more elements
A method comprising:
- forming a plurality of fully depleted silicon-on-insulator spin-transfer torque magnetoresistive random-access memory (FDSOI STT-MRAM) active word line (WL) blocks laterally separated across a memory array, each active WL block formed by:
- forming a n-type well (NW);
- forming a n-type ground plane (GP-N) layer over the NW;
- forming a buried oxide (BOX) layer over the GP-N layer;
- forming a silicon (Si) layer over the BOX layer;
- forming two pairs of two gates laterally separated over the Si layer;
- forming a shallow trench isolation (STI) region through the Si layer, BOX, and GP-N layers and a portion of the NW on opposite sides of each pair of gates;
- forming a n-type lightly dope drain (nLDD) in the Si layer on opposite sides and under a portion of each gate;
- and
- forming a n-type raised source/drain (nRSD) over each nLDD adjacent to and on opposite sides of each gate;
- forming a FDSOI STT-MRAM dummy WL block parallel to and on opposite sides of each active WL block;
- forming a plurality of source line (SL) structures laterally separated across the memory array, perpendicular to the active and dummy WL blocks;
- forming a plurality of bit line (BL) structures laterally separated across the memory array, parallel to the plurality of SL structures and perpendicular to the active and dummy WL blocks;
- connecting the plurality of SL and BL structures to the plurality of active and dummy WL blocks;
- selecting one active WL block for a write function;
- applying forward body bias (FBB) to the selected active WL block;
- and
- applying zero or reverse body bias (RBB) to all unselected active WL blocks.
15 more elements
Dependencies are inferred from the claim text.