Planar triple-implanted JFET

A method for creating a junction field-effect transistor (JFET), comprising:

• a. applying a first mask to a wafer to form a first patterned hard masking layer to the top of the wafer, the wafer comprising an upper drift region and a bottom drain region;
• b. applying three implants to an unmasked portion of the top of the wafer to form a lower gate region, a horizontal channel region, and a top gate region in an upper portion of the drift region;
• c. forming a source region in a portion of the top gate region;
• d. connecting the top and lower gate regions;
• e. forming a vertical channel region via implantation, the vertical channel region being at a distance from the source region, the vertical channel region being adjacent to, and extending through, the top gate region, the horizontal channel region, and the lower gate region, to connect to the drift region;
• and
• f. forming a lightly doped region surrounding the source region via implantation, where the lightly doped region is doped at ten percent or less of the level of doping of the source region.

A method for creating a junction field-effect transistor (JFET), comprising:

• a. applying a first mask to a wafer to form a first patterned hard masking layer to the top of the wafer, the wafer comprising an upper drift region and a bottom drain region;
• b. applying three implants to an unmasked portion of the top of the wafer to form a lower gate region, a horizontal channel region, and a top gate region in an upper portion of the drift region;
• c. forming a source region in a portion of the top gate region;
• d. connecting the top and lower gate regions;
• and
• e. forming two vertical channels via implantation, one at each end of a region comprising the upper gate, the lower gate, and the horizontal channel,
• f. wherein the vertical channels are at a distance from the source, and wherein the vertical channels abut the top gate, the horizontal channel, and the lower gate, and the drift region.