Thin-film transistor, liquid crystal display panel, and thin-film transistor manufacturing method

A thin-film transistor manufacturing method, comprising:

• providing a base plate, wherein the base plate comprises a first surface and a second surface that are opposite to each other;
• forming a gate electrode on the first surface, wherein the gate electrode comprises a first lateral face and a second lateral face and the first lateral face and the second lateral face both intersect the base plate;
• forming a gate insulation layer covering the gate electrode;
• forming a source electrode and a drain electrode that are arranged on the gate insulation layer such that a gap is formed between the source electrode and the drain electrode, wherein a distance from an end of the source electrode that faces the drain electrode to the second lateral surface is greater than a distance from the first lateral surface to the second lateral surface, and a distance from an end of the drain electrode that faces the source electrode to the first lateral surface is greater than a distance from the second lateral surface to the first lateral surface;
• forming a first ohmic contact layer, a second ohmic contact layer, and a channel layer that are on the same layer in the gap, wherein the first ohmic contact layer is arranged between the source electrode and the channel layer and two opposite ends of the first ohmic contact layer are respectively in contact engagement with the source electrode and an end of the channel layer that faces the source electrode;
• and the second ohmic contact layer is arranged between the drain electrode and the channel layer and two opposite ends of the second ohmic contact layer are respectively in contact engagement with the drain electrode and an end of the channel layer that faces the drain electrode, wherein the channel layer comprises a metal oxide layer;
• forming a passivation layer to cover the channel layer, the source electrode, the drain electrode, the first ohmic contact layer, and the second ohmic contact layer;
• forming a via in the passivation layer to correspond to the drain electrode;
• and
• forming a pixel electrode that is arranged on the passivation layer and is connected, through the via, to the drain electrode.

A thin-film transistor, comprising a base plate and a gate electrode, a gate insulation layer, a source electrode, a drain electrode, a channel layer, a first ohmic contact layer, a second ohmic contact layer, a passivation layer, and a pixel electrode that are arranged on the same side of the base plate, the gate electrode being arranged on a surface of the base plate and the gate insulation layer covering the gate electrode, the source electrode, the drain electrode, the channel layer, the first ohmic contact layer, and the second ohmic contact layer being arranged on the gate insulation layer, the source electrode and the drain electrode being spaced from each other;

• the channel layer being arranged between the source electrode and the drain electrode, the channel layer being arranged to correspond to the gate electrode, the first ohmic contact layer being arranged between the source electrode and the channel layer, two opposite ends of the first ohmic contact layer being respectively in contact engagement with an end of the source electrode that faces the channel layer and an end of the channel layer that faces the source electrode, the first ohmic contact layer functioning to reduce contact resistance between the source electrode and the channel layer, the second ohmic contact layer being arranged between the drain electrode and the channel layer, two opposite ends of the second ohmic contact layer being respectively in contact engagement with an end of the drain electrode that faces the channel layer and an end of the channel layer that faces the drain electrode, the second ohmic contact layer functioning to reduce contact resistance between the drain electrode and the channel layer, the first ohmic contact layer, the second ohmic contact layer, and the channel layer being on the same layer, the channel layer being a metal oxide layer, the passivation layer covering the channel layer, the source electrode, the drain electrode, the first ohmic contact layer, and the second ohmic contact layer, the passivation layer being formed with a via corresponding to the drain electrode, the pixel electrode being arranged on the passivation layer and connected, through the via, to the drain electrode;
• wherein the gate insulation layer comprises a first sub gate insulation layer and a second sub gate insulation layer, the first sub gate insulation layer being set on and covering the gate electrode, the second sub gate insulation layer being set on and covering the first sub gate insulation layer, the first sub gate insulation layer comprising a silicon nitride material, the second sub gate insulation layer comprising a silicon oxide material.