Metal gate and contact plug design and method forming same

A method comprising:

• forming a dummy gate stack on a top surface and a sidewall of a semiconductor fin;
• forming first gate spacers having sidewalls contacting sidewalls of the dummy gate stack;
• forming a source/drain region on a side of the dummy gate stack;
• forming an inter-layer dielectric to cover the source/drain region;
• removing the dummy gate stack to form an opening between the first gate spacers;
• forming a second gate spacer in the opening, wherein the second gate spacer has a first sidewall contacting a sidewall of one of the first gate spacers, and a second sidewall opposite to the first sidewall;
• filling a bottom portion of the opening with a replacement gate stack;
• and
• forming a gate contact plug to fill a top portion of the opening, wherein the gate contact plug is between top portions of the first gate spacers, wherein both the replacement gate stack and the gate contact plug are in contact with the second sidewall of the second gate spacer, and wherein the forming the gate contact plug comprises:
• forming a sacrificial dielectric layer over the inter-layer dielectric;
• etching the sacrificial dielectric layer to form an additional opening;
• filling a metallic material into the additional opening and the top portion of the opening;
• and
• performing a planarization on both the sacrificial dielectric layer and the metallic material, wherein the sacrificial dielectric layer is removed by the planarization.

A method comprising:

• forming gate spacers over a semiconductor region;
• forming a gate stack between the gate spacers, wherein the gate stack comprises:
• a gate dielectric comprising a bottom portion and sidewall portion over and connected to opposite ends of the bottom portion;
• and
• a gate electrode over the bottom portion of the gate dielectric;
• forming an inter-layer dielectric on opposite sides of the gate stack, with the gate spacers in the inter-layer dielectric;
• recessing the gate stack to form a recess;
• filling a dielectric material into the recess;
• planarizing the dielectric material and the gate spacers, wherein a remaining portion of the dielectric material forms a dielectric hard mask;
• etching a first portion of the dielectric hard mask to form an opening;
• forming a gate contact plug in the opening and between second portions of the dielectric hard mask, wherein the gate contact plug contacts top surfaces of the gate dielectric and the gate electrode, and wherein the forming the gate contact plug comprises:
• forming a sacrificial dielectric layer over the inter-layer dielectric;
• etching the sacrificial dielectric layer to form an additional opening;
• filling a metallic material into the additional opening and the opening;
• and
• performing a planarization on both the sacrificial dielectric layer and the metallic material, wherein the sacrificial dielectric layer is removed by the planarization;
• and
• depositing an etch stop layer, wherein a bottom surface of the etch stop layer is in contact with top surfaces of the gate spacers, the inter-layer dielectric, and the gate contact plug.