Semiconductor structure and associated fabricating method

A semiconductor structure, comprising:

• a gate structure formed on a substrate;
• a source region disposed on a first side of the gate structure and a drain region formed in the substrate on a second side of the gate structure, the source region and the drain region both having a first type of conductivity;
• a dielectric layer contiguously extending from over the gate structure over a region of the substrate extending between the second side of the gate structure and the drain region, and extending to over the drain region, wherein the dielectric layer includes at least one recess in a portion of the dielectric layer over the region of the substrate extending between the second side of the gate structure and the drain region, the at least one recess being spaced a distance from the second side of the gate toward the drain region;
• and
• an interlayer dielectric (ILD) layer formed on the substrate, the ILD layer including a first trench extending through the ILD layer to the at least one recess, wherein the first trench is substantially filled with a conductive material and a second trench extending through the ILD layer to a silicide region of the drain region, wherein the second trench is substantially filled with the conductive material.

A semiconductor structure, comprising a gate structure having gate spacers from on a substrate, wherein the gate structure has a length and a width, the greater than the length;

• a source region and a drain region formed in the substrate on either of the gate structure, wherein the drain region includes a silicide portion;
• a dielectric layer extending over a portion of the gate structure and over the drain region, wherein the dielectric layer has a plurality of the recesses in a portion of the dielectric layer that is over a region of the substrate between the gate spacers of the gate structure nearest the drain region and the silicide portion of the drain region, the plurality of recesses being collinear and being disposed along the width of the gate structure;
• a first conductive element providing contact to the silicide portion of the drain region;
• a second conductive element providing contact to the gate structure;
• and a third conductive element providing contact to the plurality of recesses, wherein portions of an interlayer dielectric (ILD) layer are between each of the first, second and third conductives.