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US 10,121,826 B1Granted
Semiconductor device and method of fabricating the same
AssigneeWinbond Electronics Corp.
InventorFrederick Chen
Life of this patent
Estimating the term…
Abstract
Provided are a semiconductor device including a plurality of transistors and a plurality of memory cells. Each of the transistors includes a gate structure and a source/drain region. The memory cells are respectively located over the gate structures. A lower electrode of each of the memory cells and an upper electrode of an adjacent memory cell are electrically connected to the source/drain region between corresponding two transistors.
Claims20
A semiconductor device comprising:
- a plurality of transistors, each of the transistors comprising a gate structure and a source/drain region;
- a plurality of memory cells respectively located over the gate structures, wherein a lower electrode of each of the memory cells and an upper electrode of an adjacent memory cell are electrically connected to the source/drain region between corresponding two transistors;
- and
- a source line, coupled to one of the memory cells through a lower electrode of the one of the memory cells and a first plug, and coupled to a corresponding one of the transistors through the lower electrode of the one of the memory cells, the first plug and a second plug, wherein the lower electrode of the one of the memory cells is physically connected to and located between the first plug and the second plug.
1 more element
A semiconductor device comprising:
- a plurality of semiconductor layers located on a substrate;
- a plurality of isolation structures located over the substrate to isolate the semiconductor layers, wherein the semiconductor layers protrude from the isolation structures;
- a plurality of gate structures respectively across at least portions of the semiconductor layers and portions of the isolation structures;
- a plurality of memory cells respectively located over the gate structures between adjacent two semiconductor layers, wherein each of the memory cells comprises a lower electrode and an upper electrode, the lower electrode of each of the memory cells is electrically connected to the upper electrode of an adjacent memory cell;
- and
- a source line, coupled to one of the memory cells through a lower electrode of the one of the memory cells and a first plug, and coupled to a corresponding one of the transistors through the lower electrode of the one of the memory cells, the first plug and a second plug, wherein the lower electrode of the one of the memory cells is physically connected to and located between the first plug and the second plug.
3 more elements
Dependencies are inferred from the claim text.