Array substrate and method for manufacturing the same and display device

A method for manufacturing an array substrate, comprising steps of:

• forming a plurality of signal lines;
• forming a connection line electrically connected to the plurality of signal lines;
• forming a first insulation layer on the plurality of signal lines and forming a first via-hole in the first insulation layer through a patterning process;
• forming a protection layer covering a portion of the connection line corresponding to a region where the first via-hole is located;
• and
• forming at least one second insulation layer on the first insulation layer with a second via-hole formed through a patterning process in each second insulation layer at a position corresponding to the first via-hole;
• wherein after the step of forming the at least one second insulation layer, the method further comprises:
• removing a portion of the protection layer corresponding to the region where the first via-hole is located;
• and
• interrupting the connection line at a position corresponding to the first via-hole, so as to interrupt electrical connection of the plurality of signal lines;
• wherein before the step of forming the at least one second insulation layer, the method further comprises:
• forming a pattern of a first conductive layer;
• wherein the first conductive layer forms the protection layer;
• wherein the array substrate is a bottom-gate thin film transistor array substrate, the signal lines comprise a plurality of gate lines and a plurality of data lines, and the connection line comprises a first connection line electrically connected to the gate lines and a second connection line electrically connected to the data lines,
• the method further comprises steps of:
• forming a gate metal layer, and forming the plurality of gate lines and the first connection line electrically connected to the gate lines through a patterning process;
• forming a gate insulation layer on the plurality of gate lines, and forming the first via-hole and a third via-hole in the gate insulation layer through a patterning process, so as to expose the first connection line at regions where the first via-hole and the third via-hole are located;
• forming a source-drain metal layer on the gate insulation layer, and forming the plurality of data lines, the second connection line electrically connected to the data lines, and the protection layer through a patterning process, a portion of the first connection line corresponding to the region where the first via-hole is located being covered by the protection layer, the second connection line being electrically connected to the first connection line through the third via-hole;
• forming a passivation layer on the source-drain metal layer, and forming the second via-hole, a fourth via-hole and a fifth via-hole in the passivation layer through a patterning process, the second via-hole being located at a position corresponding to the first via-hole, the fourth via-hole being located at a position corresponding to the third via-hole;
• removing a portion of the second connection line corresponding to a region where the fourth via-hole is located through a wet-etching process, so as to interrupt electrical connection between the second connection line and the first connection line;
• removing the protection layer and a portion of the first connection line corresponding to a region where the first via-hole is located through a wet-etching process, so as to interrupt the first connection line, thereby to interrupt electrical connection among the gate lines;
• and
• removing a portion of the second connection line corresponding to a region where the fifth via-hole is located through a wet-etching process, so as to interrupt the second connection line, thereby to interrupt electrical connection among the data lines.