TFT array substrate and manufacturing method thereof, and display device

A manufacturing method of the TFT array substrate, including:

• forming a plurality of pixel electrodes;
• forming a first metal layer comprising a first common electrode line and a plurality of gate lines, wherein the gate lines are of a double-gate-line structure in a display area, and the first common electrode line is perpendicular to the pixel electrode;
• forming a second metal layer comprising a second common electrode line on the first metal layer and a plurality of data lines, and the second common electrode line is parallel to the pixel electrode, the first common electrode line is electrically connected with the second common electrode line, and the wiring of the second common electrode line and the first common electrode line is shaped as a net on the plane;
• and
• forming a third common electrode line connected to the first common electrode line and the second common electrode line in a non-display area, wherein a same signal is in the first common electrode line, and the second common electrode line, and the third common electrode line;
• wherein the gate lines are not directly connected from the first common electrode line, and the data lines are not directly connected to the second common electrode line.

A TFT array substrate, including a display area and a non-display area,

• wherein the display area comprises:
• a pixel electrode;
• a first metal layer comprising a first common electrode line and a plurality of gate lines, wherein the gate lines are of a double-gate-line structure, and the first common electrode line is perpendicular to the pixel electrode;
• a second metal layer comprising a second common electrode line and a plurality of data lines, wherein the second common electrode lines are in parallel with the plurality of data lines, wherein the number of the plurality of data lines is reduced at least by the number of the plurality of second common electrode lines;
• and
• wherein the non-display area comprises:
• a third common electrode line connected to the first common electrode line, the second common electrode line, and an external periphery circuit;
• wherein the gate lines are not directly connected to the first common electrode line, and the data lines are not directly connected to the second common electrode line.