Semiconductor memory device

A semiconductor memory device, comprising:

• a stacked body including a plurality of control gate electrodes stacked upwardly of a substrate;
• a semiconductor layer extending along a first direction intersecting an upper surface of the substrate, the semiconductor layer facing the plurality of control gate electrodes in a second direction crossing the first direction;
• and
• a gate insulating layer provided between a control gate electrode and the semiconductor layer,
• the stacked body comprising:
• a first metal layer configuring the control gate electrode;
• a first barrier metal layer contacting an upper surface of the first metal layer;
• a first silicon nitride layer contacting an upper surface of the first barrier metal layer;
• a first inter-layer insulating layer contacting an upper surface of the first silicon nitride layer;
• a second barrier metal layer contacting a lower surface of the first metal layer;
• a second silicon nitride layer contacting a lower surface of the second barrier metal layer;
• a second inter-layer insulating layer contacting a lower surface of the second silicon nitride layer;
• and
• a third barrier metal layer formed integrally with the first barrier metal layer and the second barrier metal layer, wherein
• the third barrier metal layer contacts side surfaces of the first metal layer and the gate insulating layer, and
• a film thickness of the third barrier metal layer in the second direction is larger than a film thickness of the first barrier metal layer in the first direction and a film thickness of the second barrier metal layer in the first direction.