Semiconductor memory device

A semiconductor memory device comprising:

• a plurality of control gate electrodes laminated on a substrate;
• a first semiconductor layer that has one end connected to the substrate, has a longitudinal direction in a direction intersecting with the substrate, and is opposed to the plurality of control gate electrodes;
• an electric charge accumulating layer positioned between the first semiconductor layer and one of the plurality of control gate electrodes;
• a first contact that has one end connected to the substrate and another end connected to a source line;
• and
• a second contact that has one end connected to the substrate and another end connected to a wiring other than the source line, wherein:
• the first contact includes a first silicide layer arranged on the substrate,
• the second contact includes a second silicide layer arranged on the substrate,
• the first silicide layer has a higher temperature resistance than the second silicide layer,
• the first contact further includes:
• a third silicide layer that has a lower end connected to a top surface of the first silicide layer;
• and
• a metal layer connected to an upper end of the third silicide layer;
• and
• the semiconductor memory device further comprises a barrier metal layer arranged between the third silicide layer and the metal layer.