US 10,121,791 B2Granted

Multi-gate transistor

AssigneeSamsung Electronics Co., Ltd.

InventorsHyun Kwan Yu, Hyo Jin Kim, Dong Suk Shin, Ji Hye Yi, Ryong Ha

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Abstract

A semiconductor device includes a substrate, first through fourth gate electrodes, and first through fifth fin active pattern. A first recess which is formed in the substrate between the first and second gate electrodes intersecting the second fin active pattern, is filled with a first source/drain region, and has a first depth in a third direction perpendicular to the first and second directions. A second recess which is formed in the substrate between the third and fourth gate electrodes intersecting the second fin active pattern, is filled with a second source/drain region, and has a second depth in the third direction. A third recess which is formed in the substrate between the second and third gate electrodes intersecting the second fin active pattern, is filled with a third source/drain region, and has a third depth in the third direction. The third depth is greater than the first and second depths.

Claims20

Dependent claims

A semiconductor device comprising:

a substrate;
first through fourth gate electrodes extending in a first direction on the substrate and being sequentially separated from each other in a second direction perpendicular to the first direction;
a first fin active pattern extending in the second direction and intersecting the second and third gate electrodes;
a second fin active pattern extending in the second direction, being separated from the first fin active pattern in the first direction, and intersecting the first through fourth gate electrodes;
a third fin active pattern extending in the second direction, being separated from the second fin active pattern in the first direction, and intersecting the first and second gate electrodes;
a fourth fin active pattern extending in the second direction, being separated from the third fin active pattern in the second direction, and intersecting the third and fourth gate electrodes;
a fifth fin active pattern extending in the second direction, being separated from the third and fourth fin active patterns in the first direction, and intersecting the first through fourth gate electrodes;
a first recess in the substrate between the first and second gate electrodes intersecting the second fin active pattern, the first recess being filled with a first source/drain region, and having a first depth in a third direction perpendicular to the first and second directions;
a second recess in the substrate between the third and fourth gate electrodes intersecting the second fin active pattern, the second recess being filled with a second source/drain region, and having a second depth in the third direction;
and
a third recess which in the substrate between the second and third gate electrodes intersecting the second fin active pattern, is the third recess being filled with a third source/drain region, and having a third depth in the third direction,
wherein the third depth is greater than the first depth and the second depth.

9 more elements

A semiconductor device comprising:

a substrate comprising a first region and a second region;
a first gate electrode extending in a first direction on the first region;
a second gate electrode extending in the first direction on the first region and being separated from the first gate electrode in a second direction perpendicular to the first direction;
a third gate electrode extending in the first direction on the second region and being separated from the second gate electrode in the second direction;
a fourth gate electrode extending in the first direction on the second region and being separated from the third gate electrode in the second direction;
a first fin active pattern extending in the second direction on the first and second regions and intersecting the first through fourth gate electrodes;
a second fin active pattern extending in the second direction on the first region, being separated from the first fin active pattern in the first direction, and intersecting the first and second gate electrodes;
a third fin active pattern extending in the second direction on the second region, being separated from the second fin active pattern in the second direction, and intersecting the third and fourth gate electrodes;
a first source/drain region in the first region between the first and second gate electrodes intersecting the first fin active pattern and having a first depth in a third direction perpendicular to the first and second directions;
a second source/drain region in the second region between the third and fourth gate electrodes intersecting the first fin active pattern and having a second depth in the third direction;
and
a third source/drain region in the first and second regions between the second and third gate electrodes intersecting the first fin active pattern and having a third depth in the third direction,
wherein the third depth is greater than the first depth and the second depth.

10 more elements

A semiconductor device comprising:

a substrate comprising a first region and a second region;
a first gate electrode extending in a first direction on the first region;
a second gate electrode extending in the first direction on the first region and being separated from the first gate electrode in a second direction perpendicular to the first direction;
a third gate electrode extending in the first direction on the second region and being separated from the second gate electrode in the second direction;
a fourth gate electrode extending in the first direction on the second region and being separated from the third gate electrode in the second direction;
a plurality of fin active patterns extending in the second direction and spaced apart from each other in the first direction;
a first source drain region in the first region between the first and second gate electrodes intersecting one of the plurality of fin active patterns and having a first depth in a third direction perpendicular to the first and second directions;
a second source/drain region in the second region between the third and fourth gate electrodes intersecting the one of the plurality of fin active patterns and having a second depth in the third direction;
and
a third source/drain region in the first and second regions between the second and third gate electrodes intersecting the one of the plurality of fin active patterns and having a third depth in the third direction,
wherein the third depth is greater than the first depth and the second depth.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/819,309Filed 21 Nov 2017
Priority: KR 10-2017-001080224 Jan 2017
Published: US 2018/0211959 A126 Jul 2018
Granted: 6 Nov 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10D 84/853
Complementary IGFETs, e.g. CMOS: comprising FinFETs
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/6215
Fin field-effect transistors [FinFET]: having multiple independently-addressable gate electrodes
H10D 30/6219
Fin field-effect transistors [FinFET]: characterised by the source or drain electrodes

Family

US 2018/0211959 A1Pre-grant publication · published 26 Jul 2018
US 10,121,791 B2This patent

From the US filing history. Foreign family members aren’t listed.

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