Devices related to barrier for metallization of gallium based semiconductor

A capacitor structure comprising:

• an indium gallium phosphide layer including a ledge;
• a metal layer over the indium gallium phosphide layer, a tantalum nitride layer configured to separate and function as a barrier layer between the metal layer and the indium gallium phosphide layer;
• a gallium arsenide layer, the indium gallium phosphide layer being disposed between the gallium arsenide layer and the tantalum nitride layer;
• the gallium arsenide layer, the indium gallium phosphide layer, the metal layer, and the tantalum nitride layer being included in a metal-insulator-semiconductor capacitor;
• a contact to the gallium arsenide layer, a passivation structure being disposed laterally between the contact and the indium gallium phosphide layer;
• and
• a second metal layer connected to the contact, the second metal layer being spaced apart from the metal layer, and the tantalum nitride layer being nested within a region defined by a footprint of the second metal layer.

A semiconductor die comprising:

• a gallium arsenide layer included in a collector of a heterojunction bipolar transistor;
• a semiconductor layer that includes a wide bandgap semiconductor lattice-matched to gallium arsenide, the semiconductor layer being included in an emitter of the heterojunction bipolar transistor;
• a tantalum nitride layer over the collector and the emitter such that at least a portion of the collector and at least a portion of the emitter are within a footprint of the tantalum nitride layer;
• and
• a metal layer over the semiconductor layer, the tantalum nitride layer configured to separate and function as a barrier layer between the metal layer and the semiconductor layer.