Method of fabricating a post-passivation interconnect structure

A method of fabricating a semiconductor device, comprising:

• forming a passivation layer overlying a semiconductor substrate;
• forming a conductive layer over the semiconductor substrate and the passivation layer;
• patterning the conductive layer to form a landing pad region and a plurality of dummy regions electrically separated from the landing pad region, wherein the plurality of dummy regions surround the landing pad region in a plan view;
• depositing a conductive pillar over each of the plurality of dummy regions of the conductive layer;
• and
• forming a bump over the substrate and connected to the landing pad region, wherein each of the conductive pillars is spaced a same distance from the bump.

A method of fabricating a semiconductor device, comprising:

• forming a passivation layer overlying a semiconductor substrate;
• forming a first conductive layer over the passivation layer;
• patterning the first conductive layer to form:
• a first landing pad region and a first plurality of dummy regions electrically separated from the first landing pad region, wherein the first plurality of dummy regions surround the first landing pad region in a plan view;
• a second landing pad region and a second plurality of dummy regions electrically separated from the second landing pad region, wherein the second plurality of dummy regions surround the second landing pad region in a plan view, the second plurality of dummy regions are different than the first plurality of dummy regions;
• depositing a second conductive layer on the substrate over the first conductive layer;
• patterning the second conductive layer to form:
• a first under-bump-metallization (UBM) electrically connected to the first landing pad region, a second UBM electrically connected to the second landing pad region, a first plurality of pillars having each pillar of the first plurality of pillars overlying a respective one of the first plurality of dummy regions, and a second plurality of pillars having each pillar of the second plurality of pillars overlying a respective one of the second plurality of dummy regions;
• and
• forming a first bump over the first UBM and a second bump over the second UBM, wherein the first plurality of pillars surrounds the first bump in the plan view and the second plurality of pillars surrounds the second bump in the plan view.