US 10,121,746 B2Granted

Semiconductor device

AssigneeMurata Manufacturing Co., Ltd.

InventorsKazuya Kobayashi, Yuichi Sano, Daisuke Tokuda, Hiroaki Tokuya

Life of this patent

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Abstract

A semiconductor device includes a semiconductor substrate, a first metal layer, an insulation layer, an organic layer, and a second metal layer. The first metal layer, the insulation layer, the organic layer, and the second metal layer are sequentially stacked on a surface of the semiconductor substrate. The first metal layer and the second metal layer are electrically connected to each other through vias formed in the insulation layer and the organic layer. The second metal layer includes an electrode pad at a position corresponding to the positions of the vias. At the interface between the surface of the semiconductor substrate and the first metal layer, a patch portion having a trapezoidal cross-sectional shape is disposed directly below the vias.

Claims7

Dependent claims

A semiconductor device comprising:

a semiconductor substrate;
a first metal layer;
an inorganic insulation layer;
an organic insulation layer;
and
a second metal layer,
wherein the first metal layer, the inorganic insulation layer, the organic insulation layer, and the second metal layer are stacked on or over a surface of the semiconductor substrate,
wherein the organic insulation layer includes a hollow portion and the hollow portion is a through-hole or a blind hole,
wherein the semiconductor device further comprises a patch portion raising a bottom of the hollow portion, and the patch portion is disposed in a region between the surface of the semiconductor substrate and the hollow portion of the organic insulation layer in a thickness direction, and
wherein the patch portion has a trapezoidal cross-sectional shape, and an area of a bottom surface of the patch portion is larger than an area of an upper surface of the patch portion.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/814,833Filed 16 Nov 2017
Priority: JP 2016-22701922 Nov 2016
Published: US 2018/0145028 A124 May 2018
Granted: 6 Nov 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10W 20/435
Characterised by their conductive parts: cross-sectional shapes or dispositions of interconnections
H10W 20/42
Characterised by their conductive parts: vias, e.g. via plugs
H10W 20/47
Characterised by their insulating parts: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
H10W 72/90
Interconnections or connectors in packages: bond pads, in general

Family

US 2018/0145028 A1Pre-grant publication · published 24 May 2018
US 10,121,746 B2This patent

From the US filing history. Foreign family members aren’t listed.

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