Silicon package for embedded semiconductor chip and power converter

A method for fabricating a packaged transistor device comprising:

• providing a wafer of low-grade low-resistivity silicon (l-g-Si) including a plurality of slab sites, each site configured into ridges with a top in a first plane, the ridges framing a depression including a recessed central area in a second plane spaced from the first plane by a depth;
• forming a second insulating layer on the second silicon surface, covering all slab sites;
• removing, at each slab site, the second insulating layer from selected pads matching certain terminals of a transistor, to expose the underlying low-resistivity l-g-Si;
• depositing at least one layer of metal onto the second insulating layer and the pads of exposed l-g-Si, covering all slab sites;
• pattering the metal layer at each slab site, forming in the central site portion a plurality of pads matching the terminals of a transistor, including the power terminals, and retaining the metal on the frames as terminals;
• depositing a layer of passivation onto the patterned metal layer, covering all slab sites;
• removing, at each slab site, the passivation layer from the terminals on the ridges and from the pads in the central portion, to expose the underlying metal, while leaving un-removed the passivation material over the slopes and between the pads;
• providing a plurality of chips including transistors having terminals on the first and the second chip side, the terminals of the first chip sides including a sub-set of power terminals;
• and
• attaching the terminals of first chip sides to respective pads in the central portion of each slab site, the power terminals to the pads of exposed l-g-Si, so that the terminals of the opposite second chip side are co-planar with the metal layer of the ridges framing each central portion, whereby the slab serves as the package of the transistor device.