US 10,121,705 B2Granted

Semiconductor device and method of manufacturing the same

AssigneeRenesas Electronics Corporation

InventorsHirofumi Shinohara, Hidekazu Oda, Toshiaki Iwamatsu

Life of this patent

Estimating the term…

Loading patent…

Abstract

To suppress performance degradation of a semiconductor device, when the width of a first active region having a first field effect transistor formed therein is smaller than the width of a second active region having a second field effect transistor formed therein, the height of a surface of a first raised source layer of the first field effect transistor is made larger than the height of a surface of a second raised source layer of the second field effect transistor. Moreover, the height of a first surface of a raised drain layer of the first field effect transistor is made larger than a surface of a second raised drain layer of the second field effect transistor.

A semiconductor device comprising:

(a) a first field effect transistor formed in a first active region;
and
(b) a second field effect transistor formed in a second active region,
wherein the first field effect transistor includes:
(a1) a first source region and a first drain region which are formed in the first active region so as to be mutually spaced apart from each other;
(a2) a first channel region sandwiched between the first source region and the first drain region;
(a3) a first gate insulating film formed on the first channel region;
(a4) a first gate electrode formed on the first gate insulating film;
(a5) a first raised source layer formed on the first source region;
and
(a6) a first raised drain layer formed on the first drain region,
wherein the second field effect transistor includes:
(b1) a second source region and a second drain region which are formed in the second active region so as to be mutually spaced apart from each other;
(b2) a second channel region sandwiched between the second source region and the second drain region;
(b3) a second gate insulating film formed on the second channel region;
(b4) a second gate electrode formed on the second gate insulating film;
(b5) a second raised source layer formed on the second source region;
and
(b6) a second raised drain layer formed on the second drain region,
wherein the first active region has a width in a gate width direction of the first gate electrode that is smaller than a width of the second active region in a gate width direction of the second gate electrode,
wherein, in a cross-section view, a surface of the first raised source layer is at a height that is higher than a height of a surface of the second raised source layer, and a surface of the first raised drain layer is at a height that is higher than a height of a surface of the second raised drain layer,
wherein a width of the first raised source layer in the gate width direction of the first gate electrode is less than a width of the second raised source layer in the gate width direction of the second gate electrode, and a width of the first raised drain layer in the gate width direction of the first gate electrode is less than a width of the second raised drain layer in the gate width direction of the second gate electrode,
wherein, in a plan view, an end of the first active region in a gate length direction of the first gate electrode is bounded by a first oxide layer, and an end of the second active region in a gate length direction of the second gate electrode is bounded by a second oxide layer, and
wherein, in the plan view, a width of the first oxide layer in the gate length direction of the first gate electrode is greater than a width of the second oxide layer in the gate length direction of the second gate electrode.

21 more elements

Facts

Application

14/469,920Filed 27 Aug 2014

Priority

JP 2013-24090621 Nov 2013

Published

US 2015/0137239 A121 May 2015

Granted

6 Nov 2018

Term ends

Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10D 84/017
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their source or drain regions, e.g. silicided source or drain regions
H10B 10/12
Static random access memory [SRAM] devices: comprising a MOSFET load element
H10D 84/013
The components including insulated gates, e.g. IGFETs: manufacturing their source or drain regions, e.g. silicided source or drain regions
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe

Abstract

Claims18