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US 10,121,703 B2Granted
Contact structure and extension formation for III-V nFET
AssigneeInternational Business Machines Corporation
InventorsVeeraraghavan S. Basker, Alexander Reznicek
Life of this patent
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Abstract
FinFET devices including III-V fin structures and silicon-based source/drain regions are formed on a semiconductor substrate. Silicon is diffused into the III-V fin structures to form n-type junctions. Leakage through the substrate is addressed by forming p-n junctions adjoining the source/drain regions and isolating the III-V fin structures under the channel regions.
Claims18
A method of fabricating fin-type field-effect transistors, comprising:
- obtaining a semiconductor substrate;
- epitaxially growing a first III-V blanket layer directly on a top surface of the semiconductor substrate;
- epitaxially growing a second III-V blanket layer above the first III-V blanket layer;
- forming a plurality of III-V fin structures from the second III-V blanket layer;
- forming a plurality of gate structures on the III-V fin structures;
- forming dielectric spacers on the gate structures;
- forming a plurality of recesses through the first III-V blanket layer and the III-V fin structures down to the semiconductor substrate, thereby forming a plurality of columns extending upwardly from the semiconductor substrate, each of the columns including a III-V base formed from the first III-V blanket layer, a portion of one of the III-V fin structures, one of the plurality of gate structures, and one of the dielectric spacers;
- epitaxially growing a silicon-based semiconductor layer on an exposed surface of the semiconductor substrate and within the recesses such that a portion of the silicon-based semiconductor layer adjoins the portions of the III-V fin structures comprising each of the columns;
- subjecting the columns and the silicon-based semiconductor layer to a first annealing process, thereby causing diffusion of silicon from the silicon-based semiconductor layer into the III-V fin structures to form n-type junctions, and
- forming n-type source/drain regions from the silicon-based semiconductor layer,
- wherein epitaxially growing the silicon-based semiconductor layer further includes epitaxially growing a first, p-type silicon layer on the semiconductor substrate and having a top surface entirely beneath the portions of the III-V fin structures comprising each column and a second, undoped silicon layer on the first, p-type silicon layer, the n-type source/drain regions being formed from the second, undoped silicon layer subsequent to the first annealing process, and
- further wherein forming n-type source/drain regions from the silicon-based semiconductor layer includes implanting dopant ions within the second, undoped silicon layer and subjecting the columns and the silicon-based semiconductor layer to a second annealing process subsequent to the first annealing process, thereby causing the second, undoped silicon layer to recrystallize following ion implantation.
9 more elements
A method of fabricating fin-type field-effect transistors, comprising:
- obtaining a semiconductor substrate;
- epitaxially growing a first III-V blanket layer directly on a top surface of the semiconductor substrate;
- epitaxially growing a second III-V blanket layer above the first III-V blanket layer;
- forming a plurality of III-V fin structures from the second III-V blanket layer;
- forming a plurality of gate structures on the III-V fin structures;
- forming dielectric spacers on the gate structures;
- forming a plurality of recesses through the first III-V blanket layer and the III-V fin structures down to the semiconductor substrate, thereby forming a plurality of columns extending upwardly from the semiconductor substrate, each of the columns including a III-V base formed from the first III-V blanket layer, a portion of one of the III-V fin structures, one of the plurality of gate structures, and one of the dielectric spacers, the portions of the III-V fin structures comprising the columns including top surfaces;
- epitaxially growing a silicon-based semiconductor layer on an exposed surface of the semiconductor substrate and within the recesses such that a portion of the silicon-based semiconductor layer adjoins the portions of the III-V fin structures comprising each of the columns;
- subjecting the columns and the silicon-based semiconductor layer to a first annealing process, thereby causing diffusion of silicon from the silicon-based semiconductor layer into the III-V fin structures to form n-type junctions, and
- forming n-type source/drain regions from the silicon-based semiconductor layer,
- wherein epitaxially growing the silicon-based semiconductor layer further includes epitaxially growing a first, p-type silicon layer on the semiconductor substrate and a second, undoped silicon layer on the first, p-type silicon layer, the second, undoped silicon layer being epitaxially grown to or above the top surfaces of the portions of the III-V fin structures, the n-type source/drain regions being formed from the second, undoped silicon layer subsequent to the first annealing process, and
- further wherein forming n-type source/drain regions from the silicon-based semiconductor layer includes implanting dopant ions within the second, undoped silicon layer and subjecting the columns and the silicon-based semiconductor layer to a second annealing process subsequent to the first annealing process, thereby causing the second, undoped silicon layer to recrystallize following ion implantation.
9 more elements
A method of fabricating fin-type field-effect transistors, comprising:
- obtaining a semiconductor substrate;
- epitaxially growing a first III-V blanket layer directly on a top surface of the semiconductor substrate;
- growing a III-V semi-isolating layer on the first III-V blanket layer;
- epitaxially growing a second III-V blanket layer above the first III-V blanket layer and on the III-V semi-isolating layer;
- forming a plurality of III-V fin structures from the second III-V blanket layer;
- forming a plurality of gate structures on the III-V fin structures;
- forming dielectric spacers on the gate structures;
- forming a plurality of recesses through the first III-V blanket layer, the III-V semi-isolating layer, and the III-V fin structures down to the semiconductor substrate, thereby forming a plurality of columns extending upwardly from the semiconductor substrate, each of the columns including a III-V base formed from the first III-V blanket layer, a portion of the semi-isolating III-V layer, a portion of one of the III-V fin structures, one of the plurality of gate structures, and one of the dielectric spacers, the portion of the semi-isolating III-V layer of each column adjoining the portion of the III-V fin structure of each column;
- forming local isolation regions of III-V material on the semi-isolating III-V layer;
- epitaxially growing a silicon-based semiconductor layer on an exposed surface of the semiconductor substrate and within the recesses such that a portion of the silicon-based semiconductor layer adjoins the portions of the III-V fin structures comprising each of the columns;
- subjecting the columns and the silicon-based semiconductor layer to a first annealing process, thereby causing diffusion of silicon from the silicon-based semiconductor layer into the III-V fin structures to form n-type junctions, and
- forming n-type source/drain regions from the silicon-based semiconductor layer.
9 more elements
A method of fabricating fin-type field-effect transistors, comprising:
- obtaining a semiconductor substrate;
- epitaxially growing a first III-V blanket layer directly on a top surface of the semiconductor substrate, wherein epitaxially growing the first III-V blanket layer on the semiconductor substrate further includes growing, in order, gallium arsenide, indium phosphide and indium gallium arsenide on the semiconductor substrate, the gallium arsenide being formed directly on a top surface of the semiconductor substrate;
- growing a III-V semi-isolating layer on the first III-V blanket layer;
- epitaxially growing a second III-V blanket layer above the first III-V blanket layer and on the III-V semi-isolating layer;
- forming a plurality of III-V fin structures from the second III-V blanket layer;
- forming a plurality of gate structures on the III-V fin structures;
- forming dielectric spacers on the gate structures;
- forming a plurality of recesses through the first III-V blanket layer, the III-V semi-isolating layer, and the III-V fin structures down to the semiconductor substrate, thereby forming a plurality of columns extending upwardly from the semiconductor substrate, each of the columns including a III-V base formed from the first III-V blanket layer, a portion of one of the III-V fin structures, one of the plurality of gate structures, and one of the dielectric spacers, the portion of the semi-isolating III-V layer of each column adjoining the portion of the III-V fin structure of each column;
- epitaxially growing a silicon-based semiconductor layer on an exposed surface of the semiconductor substrate and within the recesses such that a portion of the silicon-based semiconductor layer adjoins the portions of the III-V fin structures comprising each of the columns;
- subjecting the columns and the silicon-based semiconductor layer to a first annealing process, thereby causing diffusion of silicon from the silicon-based semiconductor layer into the III-V fin structures to form n-type junctions, and
- forming n-type source/drain regions from the silicon-based semiconductor layer.
8 more elements
A method of fabricating fin-type field-effect transistors, comprising:
- obtaining a silicon-based semiconductor substrate;
- epitaxially growing a first III-V blanket layer directly on a top surface of the semiconductor substrate;
- epitaxially growing a second III-V blanket layer above the first III-V blanket layer;
- forming a plurality of III-V fin structures from the second III-V blanket layer;
- forming a plurality of gate structures on the III-V fin structures;
- forming dielectric spacers on the gate structures;
- forming a plurality of recesses by etching through the first III-V blanket layer and the III-V fin structures down to the semiconductor substrate and exposing a top surface of the semiconductor substrate, thereby forming a plurality of columns extending upwardly from the semiconductor substrate, each of the columns including a III-V base formed from the first III-V blanket layer, a portion of one of the III-V fin structures above the III-V base, one of the plurality of gate structures, and one of the dielectric spacers;
- epitaxially growing a silicon-based semiconductor layer on the exposed top surface of the semiconductor substrate and within the recesses such that an undoped portion of the silicon-based semiconductor layer adjoins the portions of the III-V fin structures comprising each of the columns;
- subjecting the columns and the silicon-based semiconductor layer to a first annealing process, thereby causing diffusion of silicon from the undoped portion of the silicon-based semiconductor layer into the III-V fin structures and diffusion of a group V element from the III-V fin structures into the undoped portion of the silicon-based semiconductor layer to form n-type junctions, and
- introducing dopant ions to the undoped portion of the silicon-based semiconductor layer to form n-type source/drain regions adjoining the n-type junctions from the undoped portion of the silicon-based semiconductor layer.
7 more elements
Dependencies are inferred from the claim text.