Package substrate first-level-interconnect architecture

An integrated circuit (IC) package, comprising:

• a package substrate, wherein the package substrate includes,
• a dielectric layer having a dielectric surface that is planarized;
• a via buried in the dielectric layer, wherein the via includes a via surface that is exposed on the dielectric surface, and wherein the via surface is planarized;
• and
• a bond pad on the dielectric surface, wherein a first thickness of the bond pad includes a surface finish on the via surface, and wherein a second thickness of the bond pad includes a plating stack on the surface finish, wherein the plating stack is a nickel-palladium-gold stack, and wherein the nickel is in direct contact on top of the surface finish, the palladium is in direct contact on top of the nickel, and the gold is in direct contact on top of the palladium;
• a die that includes an IC pad;
• and
• a solder ball coupled with the bond pad and the IC pad, to form a first level interconnect between the package substrate and the die.

A method of producing a package substrate, comprising:

• creating a via on a pad;
• burying the via in a dielectric applied over the via and the pad;
• planarizing the dielectric to reveal a top of the via through a flat surface of the dielectric;
• depositing a seed layer over the flat surface, wherein the seed layer is to cover the via;
• and
• plating a nickel-palladium-gold (NPG) stack on the seed layer over the via, wherein the nickel is in direct contact on the seed layer, the palladium is in direct contact on the nickel, and the gold is in direct contact on the palladium, and wherein the seed layer and the NPG stack form a bond pad on the via.

A package substrate, comprising:

• a layer having a layer surface that is planarized;
• a via within the layer, wherein the via includes a via surface that is exposed on the layer surface, and wherein the via surface is planarized;
• and
• a bond pad on the layer surface, wherein a first thickness of the bond pad includes a seed layer on the via surface, and wherein a second thickness of the bond pad includes a plating stack on the seed layer, wherein the plating stack is a cobalt/tungsten alloy-palladium-gold stack, and wherein the cobalt/tungsten alloy is in direct contact on the seed layer, the palladium is in direct contact on the cobalt/tungsten alloy, and the gold is in direct contact on the palladium.