Semiconductor device and a method for fabricating the same

A method of manufacturing a semiconductor device, the method comprising:

• forming an interlayer dielectric (ILD) layer over an underlying structure, the underlying structure including:
• first to fourth gate structures, each having a metal gate, sidewall spacers disposed on opposing sides of the metal gate and a cap insulating layer disposed over the metal gate, the first to fourth gate structures being arranged in this order along a first direction;
• a first source/drain (S/D) epitaxial layer and a second S/D epitaxial layer, both disposed between the second gate structure and the third gate structure;
• and
• an etching-stop layer (ESL) covering the first and second S/D epitaxial layers;
• forming a first opening in the ILD layer by etching over an area including a region between the first and second S/D epitaxial layer;
• forming a dielectric filling layer in the first opening;
• removing, by using wet etching, the ILD layer disposed above the first and second S/D epitaxial layers, thereby forming a second opening and a third opening, respectively, and the ILD layer disposed between the first gate structure and the second gate structure, thereby forming a fourth opening;
• removing the ESL disposed on the first and second S/D epitaxial layers, thereby at least partially exposing the first and second S/D epitaxial layers;
• and
• forming a conductive material over the exposed first and second S/D epitaxial layers, thereby forming a first S/D contact on the first S/D epitaxial layer and a second S/D contact on the second S/D epitaxial layer, and in the fourth opening, thereby forming a contact bar.

A method of manufacturing a semiconductor device, the method comprising:

• forming an interlayer dielectric (ILD) layer over an underlying structure, the underlying structure including:
• a first gate structure and a second gate structure, each of which includes a metal gate and a cap insulating layer disposed over the metal gate;
• source/drain epitaxial layers disposed between the first and second gate structures;
• and
• an etching-stop layer (ESL) covering the source/drain epitaxial layers;
• forming openings in the ILD layer by etching, the openings partially overlapping source/drain epitaxial layers, in plan view;
• forming a dielectric filling layer in the openings;
• removing, by using wet etching, the ILD layer disposed above the source/drain epitaxial layers;
• removing the ESL disposed on the source/drain epitaxial layers, thereby at least partially exposing the source/drain epitaxial layers;
• and
• forming a conductive material over the exposed source/drain epitaxial layers.