Flash memory fabrication method
AssigneeSemiconductor Manufacturing International (Shanghai) Corporation
InventorJinhua Liu
Life of this patent
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Abstract
A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate comprising an active region, and successive layers of a tunnel oxide layer, a floating gate, a gate dielectric layer, a control gate overlying each other. A first portion of the tunnel oxide layer disposed on an edge of the active region has a thickness that is greater than a thickness of a second portion of the tunnel oxide layer disposed away from the edge of the active region. Such features ensure efficient reduction of read disturb errors of a Flash memory device.
Claims15
A semiconductor device comprising:
- a semiconductor substrate comprising an active region;
- a tunnel oxide layer overlying the semiconductor substrate;
- a shallow trench isolation structure disposed at opposite sides of the active region and having an upper surface flush with an upper surface of the semiconductor substrate;
- a tunnel oxide thickness enhancing region disposed along a side surface of the shallow trench isolation structure adjacent to the active region and having an upper surface flush with an upper surface of the shallow trench isolation structure;
- a floating gate overlying the tunnel oxide layer;
- a gate dielectric layer overlying the floating gate;
- and
- a control gate overlying the gate dielectric layer,
- wherein a first portion of the tunnel oxide layer disposed on an edge of the active region and on the tunnel oxide thickness enhancing region has a thickness greater than a thickness of a second portion of the tunnel oxide layer disposed away from the edge of the active region, wherein the tunnel oxide thickness enhancing region is disposed below the first position of the tunnel oxide layer and spaced apart from the second portion of the tunnel oxide layer.
A method for manufacturing a semiconductor device, the method comprising:
- providing a semiconductor substrate comprising an active region;
- forming a hard mask on the semiconductor substrate;
- etching the semiconductor substrate using the hard mask as a mask to form a trench;
- performing an ion implantation onto the semiconductor layer to form a tunnel oxide thickness enhancing region along a side surface of the trench and adjacent to the active region;
- forming a shallow trench isolation structure in the trench on the tunnel oxide thickness enhancing region;
- removing the hard mask;
- forming a tunnel oxide layer in a location previously occupied by the hard mask, wherein a first portion of the tunnel oxide layer disposed on the edge of the active region and on the tunnel oxide thickness enhancing region has a thickness greater than a thickness of a second portion of the tunnel oxide layer disposed away from the edge of the active region;
- and
- forming a floating gate on the tunnel oxide layer.
An electronic device comprising an electronic component and a semiconductor device electrically connected with the electronic component, the semiconductor device comprising:
- a semiconductor substrate comprising an active region;
- a tunnel oxide layer overlying the semiconductor substrate;
- a shallow trench isolation structure disposed at opposite sides of the active region and having an upper surface flush with an upper surface of the semiconductor substrate;
- a tunnel oxide thickness enhancing region disposed along a side surface of the shallow trench isolation structure adjacent to the active region and having an upper surface flush with an upper surface of the shallow trench isolation structure;
- a floating gate overlying the tunnel oxide layer;
- a gate dielectric layer overlying the floating gate;
- and
- a control gate overlying the gate dielectric layer,
- wherein a first portion of the tunnel oxide layer disposed on an edge of the active region and on the tunnel oxide thickness enhancing region has a thickness greater than a thickness of a second portion of the tunnel oxide layer disposed away from the edge of the active region, wherein the tunnel oxide thickness enhancing region is disposed below the first position of the tunnel oxide layer and spaced apart from the second portion of the tunnel oxide layer.
Dependencies are inferred from the claim text.