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US 10,121,668 B2Granted
Method of forming closed cell lateral MOSFET using silicide source
AssigneeAlpha and Omega Semiconductor Incorporated
InventorShekar Mallikarjunaswamy
Life of this patent
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Abstract
A closed cell lateral MOSFET device includes minimally sized source/body contacts formed in source cells with silicided source and body diffusion regions formed therein. In this manner, the cell pitch of the cellular transistor array is kept small while the ruggedness of the transistor is ensured. In other embodiments, a closed cell lateral MOSFET device is formed using silicided source and body diffusion regions and self-aligned contacts or borderless contacts as the source/body contacts. The polysilicon gate mesh can be formed using minimum polysilicon-to-polysilicon spacing to minimize the cell pitch of the cellular transistor array.
Claims18
A method for forming a closed cell lateral MOS transistor, comprising:
- providing a semiconductor layer of a first conductivity type forming the body of the transistor and being lightly doped;
- forming a conductive gate overlying and insulated from a top surface of the semiconductor layer by a gate dielectric layer, the conductive gate forming a mesh having a plurality of openings, the plurality of openings defining a cellular array of source cells and drain cells;
- forming sidewall spacers on sidewalls of the conductive gate;
- forming a plurality of diffusion regions of a second conductivity type, opposite the first conductivity type, in the semiconductor layer exposed by the openings in the mesh, the plurality of diffusion regions forming the cellular array of source cells and drain cells, wherein alternating rows of the diffusion regions form source regions and drain regions of the transistor, and the semiconductor layer under the conductive gate between the source regions and the drain regions forms the channel of the transistor;
- forming a body diffusion region of the first conductivity type in each of source cells in the cellular array of source and drain cells, the body diffusion region being more heavily doped than the semiconductor layer and being encircled by the source region in each of the source cell, wherein the body diffusion region is formed centered in the source cell surrounded by the source region;
- forming a metal silicide layer on a top surface of the plurality of diffusion regions and the body diffusion regions, the metal silicide layer being formed in the source cells to electrically connect the source region and the body diffusion region formed in each of the source cells;
- and
- forming a source/body contact in each of the source cells and in contact with the metal silicide layer, the source/body contact being electrically connected to the source region and the body diffusion region in each of the source cells through the metal silicide layer, wherein the source/body contact is positioned above the body diffusion region only in the source cell and the source/body contact has a dimension smaller than a dimension of the body diffusion region in the source cell at the top surface of the semiconductor layer, and wherein the sidewall spacer is positioned between the conductive gate and the metal silicide layer, and the source/body contact is separated from the sidewall spacer by a dielectric material,
- wherein the source/body contact in each of the source cells comprises a contact having minimally sized dimension and minimal spacing to the conductive gate surrounding the respective source cell.
6 more elements
A method for forming a closed cell lateral MOS transistor, comprising:
- providing a semiconductor layer of a first conductivity type forming the body of the transistor, the semiconductor layer being lightly doped;
- forming a conductive gate overlying and insulated from a top surface of the semiconductor layer by a gate dielectric layer, the conductive gate forming a mesh having a plurality of openings, the plurality of openings defining a cellular array of source cells and drain cells;
- forming sidewall spacers on sidewalls of the conductive gate;
- forming a plurality of diffusion regions of a second conductivity type, opposite the first conductivity type, in the semiconductor layer exposed by the openings in the mesh, the plurality of diffusion regions forming the cellular array of source cells and drain cells, wherein alternating rows of the diffusion regions form source regions and drain regions of the transistor, and the semiconductor layer under the conductive gate between the source regions and the drain regions forms the channel of the transistor;
- forming a body diffusion region of the first conductivity type in each of the source cells in the cellular array of source and drain cells, the body diffusion region being more heavily doped than the semiconductor layer and being encircled by the source region in each of the source cell;
- forming a metal silicide layer on a top surface of the plurality of diffusion regions and the body diffusion regions, the metal silicide layer being formed in the source cells to electrically connect the source region and the body diffusion region formed in each of the source cells;
- forming a dielectric layer formed over the semiconductor layer, the conductive gate and the sidewall spacers, the dielectric layer including a plurality of contact openings exposing at least the source cells, each contact opening being formed in a respective source cell to expose at least a portion of the source region and at least a portion of the body region formed in the respective source cell, and at least one sidewall of the contact opening overlapping the sidewall spacer formed on at least one sidewall of the conductive gate to expose a lower portion of the sidewall spacer;
- and
- forming a source/body contact in the contact opening of each of the source cells and in contact with the metal silicide layer, the source/body contact being electrically connected to the source region and the body diffusion region in each of the source cells through the metal silicide layer, the source/body contact being isolated from the conductive gate by the sidewall spacers.
6 more elements
Dependencies are inferred from the claim text.