Digital electron amplifier with anode readout devices and methods of fabrication
AssigneeUchicago Argonne, LLC
InventorsAnil U. Mane, Jeffrey W. Elam
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Abstract
Scalable electron amplifier devices and methods of fabricating the devices an atomic layer deposition (“ALD”) fabrication process are described. The ALD fabrication process allows for large area (e.g., eight inches by eight inches) electron amplifier devices to be produced at reduced costs compared to current fabrication processes. The ALD fabrication process allows for nanostructure functional coatings, to impart a desired electrical conductivity and electron emissivity onto low cost borosilicate glass micro-capillary arrays to form the electron amplifier devices.
Claims14
A method of fabricating a digital electron amplifier system on chip, the method comprising:
- providing a base substrate having a top surface;
- depositing an insulating layer on the top surface of the base substrate;
- providing an anode structure on top of the insulating layer;
- depositing an insulating oxide layer on top of the anode structure;
- forming an electron amplification structure (“EAS”) on top of the insulating oxide layer, the EAS having a bottom electrical contact, a top electrical contact, and a resistive layer positioned in between the bottom electrical contact and the top electrical contact;
- and
- forming electron amplification pores, each of the electron amplification pores passing through the top electrical contact, the resistive layer, the bottom electrical contact, and the insulating oxide layer thereby exposing the anode structure at a bottom of each of the electron amplification pores and each of the electron amplification pores defined by an electron amplification pore wall;
- and
- depositing a secondary electron emission (“SEE”) layer on the each of the electron amplification pore walls, the SEE layer selected from a material configured to emit secondary electrons when a primary electron impacts the SEE layer while a bias voltage is applied across the SEE layer.
A method of fabricating a secondary electron emission layer within electron amplification pores, the method comprising:
- forming an electron amplification structure (“EAS”) on top of an insulating oxide layer of an anode structure, the EAS having a bottom electrical contact, a top electrical contact, and a resistive layer positioned in between the bottom electrical contact and the top electrical contact;
- and
- forming electron amplification pores, each of the electron amplification pores passing through the top electrical contact, the resistive layer, the bottom electrical contact, and the insulating oxide layer thereby exposing the anode structure at a bottom of each of the electron amplification pores and each of the electron amplification pores defined by an electron amplification pore wall;
- depositing a secondary electron emission (“SEE”) layer uniformly on the each of the electron amplification pore walls, the SEE layer selected from a material configured to emit secondary electrons when a primary electron impacts the SEE layer while a bias voltage is applied across the SEE layer.
Dependencies are inferred from the claim text.