Designing method of semiconductor device and semiconductor device

A semiconductor device comprising a memory circuit with a memory built-in self test circuit therein,

• the memory circuit including:
• a pulse generator;
• a plurality of input and output circuits configured to input and output data and being arranged adjacently to the pulse generator in a first direction and each of the plurality of input and output circuits being corresponding to each of bits of the data to be inputted and outputted;
• a pattern generator of the memory built-in self test circuit configured to perform generation of a test pattern and being arranged adjacently to the pulse generator in a second direction different from the first direction, between the pattern generator and the pulse generator wiring of a signal to be transmitted being connected by being arranged adjacently to the pulse generator;
• and
• a same number of a plurality of comparators of the memory built-in self test circuit as a number of the plurality of input and output circuits, each of the plurality of comparators being configured to compare an output value to be supplied from each of the input and output circuits respectively and an expected value to be supplied from the pattern generator, the plurality of comparators being arranged adjacently to the plurality of input and output circuits in the second direction with a same pitch as a pitch of the plurality of input and output circuits, between the plurality of comparators and the plurality of input and output circuits wirings of signals to be transmitted being connected by being arranged adjacently to the plurality of input and output circuits.